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1.发明授权Microprocessor, method and computer program product for direct page prefetch in millicode capable computer system 有权微处理器，方法和计算机程序产品，用于在具有计算机能力的计算机系统中进行直接页面预取公开(公告)号：US08549255B2
公开(公告)日：2013-10-01
申请号：US12032041
申请日：2008-02-15
申请人： David A. Schroter , Mark S. Farrell , Jennifer Navarro , Chung-Lung Kevin Shum , Charles F. Webb
发明人： David A. Schroter , Mark S. Farrell , Jennifer Navarro , Chung-Lung Kevin Shum , Charles F. Webb
IPC分类号： G06F12/00
CPC分类号： G06F9/30047 , G06F12/0862
摘要： A microprocessor equipped to provide hardware initiated prefetching, includes at least one architecture for performing: issuance of a prefetch instruction; writing of a prefetch address into a prefetch fetch address register (PFAR); attempting a prefetch according to the address; detecting one of a cache miss and a cache hit; and if there is a cache miss, then sending a miss request to a next cache level and attempting cache access in a non-busy cycle; and if there is a cache hit, then incrementing the address in the PFAR and completing the prefetch. A method and a computer program product are provided.
摘要翻译： 配备提供硬件发起预取的微处理器包括用于执行：发出预取指令的至少一个架构; 将预取地址写入预取提取地址寄存器（PFAR）; 根据地址尝试预取; 检测缓存未命中和缓存命中之一; 并且如果存在高速缓存未命中，则将错误请求发送到下一个高速缓存级别，并在非繁忙周期中尝试高速缓存访问; 并且如果存在缓存命中，则增加PFAR中的地址并完成预取。 提供了一种方法和计算机程序产品。
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2.发明申请MICROPROCESSOR, METHOD AND COMPUTER PROGRAM PRODUCT FOR DIRECT PAGE PREFETCH IN MILLICODE CAPABLE COMPUTER SYSTEM 有权MICROPROCESSOR，方法和计算机程序产品，用于在MILLICODE可编程计算机系统中直接提取公开(公告)号：US20090210662A1
公开(公告)日：2009-08-20
申请号：US12032041
申请日：2008-02-15
申请人： David A. Schroter , Mark S. Farrell , Jennifer Navarro , Chung-Lung Kevin Shum , Charles F. Webb
发明人： David A. Schroter , Mark S. Farrell , Jennifer Navarro , Chung-Lung Kevin Shum , Charles F. Webb
CPC分类号： G06F9/30047 , G06F12/0862
摘要： A microprocessor equipped to provide hardware initiated prefetching, includes at least one architecture for performing: issuance of a prefetch instruction; writing of a prefetch address into a prefetch fetch address register (PFAR); attempting a prefetch according to the address; detecting one of a cache miss and a cache hit; and if there is a cache miss, then sending a miss request to a next cache level and attempting cache access in a non-busy cycle; and if there is a cache hit, then incrementing the address in the PFAR and completing the prefetch. A method and a computer program product are provided.
摘要翻译： 配备提供硬件发起预取的微处理器包括用于执行：发出预取指令的至少一个架构; 将预取地址写入预取提取地址寄存器（PFAR）; 根据地址尝试预取; 检测缓存未命中和缓存命中之一; 并且如果存在高速缓存未命中，则将错误请求发送到下一个高速缓存级别，并在非繁忙周期中尝试高速缓存访问; 并且如果存在缓存命中，则增加PFAR中的地址并完成预取。 提供了一种方法和计算机程序产品。
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3.发明授权Re-fetch of long operand buffered remainder after cache line invalidation in out-of-order multiprocessor system without instruction re-execution 失效在无指令重新执行的无序多处理器系统中，在高速缓存行无效之后重新获取长操作数缓冲余数公开(公告)号：US07089408B2
公开(公告)日：2006-08-08
申请号：US10435879
申请日：2003-05-12
IPC分类号： G06F9/34
CPC分类号： G06F9/383 , G06F9/3861
摘要： A system and method to re-fetch operand data lost for instructions with operands greater than eight bytes in length due to line invalidation due to storage update from a single or plurality of processors in a multiprocessor computer system using microprocessors that perform out of order operand fetch with respect to sequential program order in which it is not possible or desirable to kill the execution of the instruction when the storage access rules require that it appear that the operand data is accessed in program execution order.
摘要翻译： 由于多处理器计算机系统中的单个或多个处理器的存储更新导致线路无效，因此使用执行无序操作数获取的微处理器，重新获取长度大于8字节的指令的操作数丢失的系统和方法 关于顺序程序顺序，其中当存储访问规则要求看起来以程序执行顺序访问操作数数据时，不可能或不希望地杀死指令的执行。
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