Clock synchronization in a multistage switch structure
    3.
    发明申请
    Clock synchronization in a multistage switch structure 审中-公开
    多级开关结构中的时钟同步

    公开(公告)号:US20060209901A1

    公开(公告)日:2006-09-21

    申请号:US11304390

    申请日:2005-12-14

    Applicant: Jeong-in Kim

    Inventor: Jeong-in Kim

    Abstract: A clock synchronizing method in a multistage switch structure comprises providing a first reference clock signal to a first switch via a first clock recovery unit; providing a second reference clock signal to a second switch via a Phase Lock Loop (PLL); and providing a third reference clock signal to a third switch via a second clock recovery unit to synchronize first, second and third switches.

    Abstract translation: 多级开关结构中的时钟同步方法包括经由第一时钟恢复单元向第一开关提供第一参考时钟信号; 通过锁相环(PLL)向第二开关提供第二参考时钟信号; 以及经由第二时钟恢复单元向第三开关提供第三参考时钟信号以同步第一,第二和第三开关。

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