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公开(公告)号:US20060022714A1
公开(公告)日:2006-02-02
申请号:US10902204
申请日:2004-07-29
IPC分类号: H03K19/096
CPC分类号: H03K19/0963
摘要: A circuit (50) that receives dynamic signals performs both logic and latching to achieve high speed operation. The circuit has a clock that defines both an evaluation phase and a precharge phase in which the dynamic signals are evaluated during the evaluation phase. The circuit (50) functions by precharging a latch node (INT) during the evaluation phase then performing evaluation as well during the evaluation phase. The evaluation results in providing a valid logic state to the latch node. A latch circuit (54) latches this valid state during the precharge phase and holds it in this valid state during the precharge phase. This can be adapted to select which one of the dynamic signals is to be coupled and latched on the latch node (INT).
摘要翻译: 接收动态信号的电路(50)执行逻辑和锁存以实现高速操作。 电路具有定义评估阶段和预充电阶段的时钟,其中动态信号在评估阶段被评估。 电路(50)通过在评估阶段期间对锁存节点(INT)进行预充电来起作用,然后在评估阶段期间执行评估。 评估导致向锁存节点提供有效的逻辑状态。 锁存电路(54)在预充电阶段期间锁存该有效状态,并且在预充电阶段将其保持在该有效状态。 这可以适于选择哪个动态信号被耦合并锁存在锁存节点(INT)上。
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公开(公告)号:US20080022047A1
公开(公告)日:2008-01-24
申请号:US11865495
申请日:2007-10-01
IPC分类号: G06F12/00
CPC分类号: G11C11/412 , G11C15/00
摘要: Storage circuits (180-183 and 280-281) may be used for low power operation while allowing fast read access. In one embodiment (e.g. circuit 100), shared complementary write bit lines (101, 102), separate read bit lines (103-106), a shared read word line (107), and separate write word lines (108-111) are used. In an alternate embodiment (e.g. circuit 200), shared complementary write bit lines (201, 202), a shared read bit line (203), separate read word lines (206-207), and separate write word lines (208-209) are used. The storage circuit may be used in a variety of contexts, such as, for example, a register file (17), a branch unit (15), an SRAM (19), other modules (20), a cache (18), a buffer (21), and/or a memory (14).
摘要翻译: 存储电路(180 - 183和280 - 281)可用于低功耗操作,同时允许快速读取访问。 在一个实施例中(例如电路100),共享互补写位线(101,102),分离读位线(103-106),共享读字线(107)和单独写字线(108-111) 用过的。 在另一实施例(例如电路200)中,共享互补写位线(201,202),共享读位线(203),分离读字线(206-207)和单独写字线(208-209) 被使用。 存储电路可以用于各种上下文中,例如寄存器文件(17),分支单元(15),SRAM(19),其他模块(20),高速缓存(18), 缓冲器(21)和/或存储器(14)。
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公开(公告)号:US20060262633A1
公开(公告)日:2006-11-23
申请号:US11132457
申请日:2005-05-19
IPC分类号: G11C8/00
CPC分类号: G11C11/412 , G11C15/00
摘要: Storage circuits (180-183 and 280-281) may be used for low power operation while allowing fast read access. In one embodiment (e.g. circuit 100), shared complementary write bit lines (101, 102), separate read bit lines (103-106), a shared read word line (107), and separate write word lines (108-111) are used. In an alternate embodiment (e.g. circuit 200), shared complementary write bit lines (201, 202), a shared read bit line (203), separate read word lines (206-207), and separate write word lines (208-209) are used. The storage circuit may be used in a variety of contexts, such as, for example, a register file (17), a branch unit (15), an SRAM (19), other modules (20), a cache (18), a buffer (21), and/or a memory (14).
摘要翻译: 存储电路(180 - 183和280 - 281)可用于低功耗操作,同时允许快速读取访问。 在一个实施例中(例如电路100),共享互补写位线(101,102),分离读位线(103-106),共享读字线(107)和单独写字线(108-111) 用过的。 在另一实施例(例如电路200)中,共享互补写位线(201,202),共享读位线(203),分离读字线(206-207)和单独写字线(208-209) 被使用。 存储电路可以用于各种上下文中,例如寄存器文件(17),分支单元(15),SRAM(19),其他模块(20),高速缓存(18), 缓冲器(21)和/或存储器(14)。
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公开(公告)号:US20050040856A1
公开(公告)日:2005-02-24
申请号:US10646081
申请日:2003-08-22
CPC分类号: H03K3/356121
摘要: A circuit provides latched data in a domino circuit environment. The circuit receives a pair of input signals that are either in complementary logic states, which is data, or in the same logic state, which is the reset condition. The circuit responds to the complementary logic states by providing intermediate signals and output signals in corresponding complementary logic states. The intermediate logic states are latched by cross-coupled clocked inverters prior to the pair of signals switching from data to reset. The intermediate signals are thus latched in the complementary logic states that correspond to data even after the pair of input signals have returned to reset. The output signals are also thus provided in complementary logic states that correspond to data prior to the input signals being reset.
摘要翻译: 电路在多米诺骨牌电路环境中提供锁存数据。 该电路接收一对输入信号,该输入信号处于作为复位条件的互补逻辑状态,即是数据或处于相同的逻辑状态。 电路通过提供相应的互补逻辑状态的中间信号和输出信号来响应互补逻辑状态。 在将数据从数据切换到复位之前,中间逻辑状态由交叉耦合的时钟反相器锁存。 因此,即使在一对输入信号已经返回到复位之后,中间信号也被锁存在与数据相对应的互补逻辑状态中。 因此,输出信号也被提供在与输入信号被复位之前的数据相对应的互补逻辑状态中。
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