摘要:
An FFT circuit is implemented using a radix-4 butterfly element and a partitioned memory for storage of a prescribed number of data values. The radix-4 butterfly element is configured for performing an FFT operation in a prescribed number of stages, each stage including a prescribed number of in-place computation operations relative to the prescribed number of data values. The partitioned memory includes a first memory portion and a second memory portion, and the data values for the FFT circuit are divided equally for storage in the first and second memory portions in a manner that ensures that each in-place computation operation is based on retrieval of an equal number of data values retrieved from each of the first and second memory portions.
摘要:
A channel estimator, configured for supplying equalization coefficients to a frequency equalizer, is configured for determining equalizer coefficients for a received wireless signal based on a minimum equalization error-based estimation. The channel estimator is configured for identifying first and second long preambles from the received wireless signal, determining an equalization coefficient for a selected frequency based on a minimized cost function for the first and second long preambles relative to a prescribed preamble value for the selected frequency, and supplying the equalization coefficient for the selected frequency to a frequency equalizer for equalization of the received wireless signal.