公开(公告)号：US20130070881A1

公开(公告)日：2013-03-21

申请号：US13609749

申请日：2012-09-11

Applicant: Cheng-Chieh Lin ,  Jian-Yu Ding ,  Yao-Chi Wang

Inventor： Cheng-Chieh Lin ,  Jian-Yu Ding ,  Yao-Chi Wang

IPC: H04L7/04

CPC classification number: H03L7/1976 ,  H03L7/099 ,  H03L7/104 ,  H03L2207/06

Abstract: A phase locked loop and an associated alignment method are provided. A disclosed phase locked loop receives a reference signal to provide a feedback signal. The phase locked loop is first opened. When the phase locked loop is open, a frequency range of an oscillating signal from a voltage-controlled oscillator is substantially selected. The feedback signal is provided according to the oscillation signal. After the frequency range is selected, the phase locked loop is kept open and the phases of the reference signal and the feedback signal are substantially aligned. The phase locked loop is then closed after the reference signal and the feedback signal are aligned.

Abstract translation: 提供了锁相环和相关对准方法。 所公开的锁相环接收参考信号以提供反馈信号。 首先打开锁相环。 当锁相环断开时，基本上选择来自压控振荡器的振荡信号的频率范围。 根据振荡信号提供反馈信号。 选择频率范围后，锁相环保持断开，参考信号和反馈信号的相位基本对齐。 然后在参考信号和反馈信号对齐后，闭锁环路。

公开(公告)号：US20090213980A1

公开(公告)日：2009-08-27

申请号：US12363792

申请日：2009-02-02

Applicant: Jian-Yu Ding ,  Shen-Ching Sun ,  Yao-Chi Wang ,  Chao-Tung Yang ,  Fucheng Wang ,  Shuo-Yuan Hsiao

Inventor： Jian-Yu Ding ,  Shen-Ching Sun ,  Yao-Chi Wang ,  Chao-Tung Yang ,  Fucheng Wang ,  Shuo-Yuan Hsiao

IPC: H03K21/00

CPC classification number: H03K23/584 ,  H03K23/665 ,  H03K23/667 ,  H03L7/193 ,  H03L7/1976

Abstract: A multi-modulus divider and a method for performing frequency dividing by utilizing a multi-modulus divider are disclosed. The multi-modulus divider comprises a multi-modulus dividing circuit, a pulse generating circuit, and a modulus signal generating circuit. The multi-modulus dividing circuit comprises several serially connected divider cells, of which a predetermined one may be bypassed. The multi-modulus dividing circuit generates an output frequency according to an input frequency and a divisor. A range of the divisor comprises a plurality of numerical intervals. The pulse generating circuit generates a pulse signal. The modulus signal generating circuit generates a determination result by determining which numerical interval the divisor belongs to, and inputs, according to the determination result, the pulse signal into the predetermined divider cell to be one of references which the predetermined divider cell refers to when outputting a modulus signal. The predetermined divider cell corresponds to the determination result.

Abstract translation: 公开了一种使用多模式分频器进行分频的多模式分频器和方法。 多模式分配器包括多模式分频电路，脉冲发生电路和模数信号发生电路。 多模式分频电路包括几个串联的分频器单元，其中预定的分频器可以被旁路。 多模式分频电路根据输入频率和除数产生输出频率。 除数的范围包括多个数字间隔。 脉冲发生电路产生脉冲信号。 模数信号发生电路通过确定除数属于哪个数值间隔来产生确定结果，并且根据确定结果将预定分频器单元中的脉冲信号输入为当输出时预定分频单元参考的参考之一 模数信号。 预定的分频器单元对应于确定结果。

公开(公告)号：US08599997B2

公开(公告)日：2013-12-03

申请号：US13556392

申请日：2012-07-24

Applicant: Yen-Tso Chen ,  Jian-Yu Ding

Inventor： Yen-Tso Chen ,  Jian-Yu Ding

IPC: H03K21/00 ,  H03K23/00

CPC classification number: H03K23/662 ,  H03K23/667

Abstract: A multiple-modulus divider and an associated control method are provided. The multiple-modulus divider includes a divisor loader, a multiple-modulus dividing circuit and a modulus controller. The divisor loader downloads a divisor when a download signal indicates a start of a division period. The multiple-modulus circuit includes a plurality of cascaded divisors, and provides an output frequency according to an input frequency and the divisor. The dividers respectively output a plurality of modulus output signals, and each is operable under either a close-loop state or an open-loop state. The modulus controller selects and controls one of the dividers according to the divisor, and ensures the selected divider is maintained at the open-loop state when the division period ends. The download signal corresponds to one of the modulus output signals.

Abstract translation: 提供了一个多模式分频器和相关的控制方法。 多模式分配器包括除数加载器，多模式分割电路和模数控制器。 当下载信号指示分割期间的开始时，除数加载器下载除数。 多模电路包括多个级联除数，并根据输入频率和除数提供输出频率。 分频器分别输出多个模数输出信号，并且每个可在闭环状态或开环状态下操作。 模数控制器根据除数选择和控制一个分频器，并且在分频周期结束时确保所选择的分频器保持在开环状态。 下载信号对应于模数输出信号之一。

公开(公告)号：US20100141347A1

公开(公告)日：2010-06-10

申请号：US12485513

申请日：2009-06-16

Applicant: SHUO YUAN HSIAO ,  YAO-CHI WANG ,  SHEN-CHING SUN ,  JIAN-YU DING

Inventor： SHUO YUAN HSIAO ,  YAO-CHI WANG ,  SHEN-CHING SUN ,  JIAN-YU DING

IPC: H03L5/00

CPC classification number: H03L7/113 ,  H03L1/022 ,  H03L7/0891 ,  H03L7/18

Abstract: A band selecting method applied to a voltage controlled oscillator (VCO) of a phase locked loop (PLL) and an associated method is provided. The band selecting method generates an open-loop control voltage according to a temperature signal; inputting the open-loop control voltage into the VCO; switching sequentially between a plurality of frequency bands of the VCO and generating a plurality of voltage controlled signals for the frequency bands; selecting a preferred voltage controlled signal and its corresponding frequency band as an operating band for the PLL.

Abstract translation: 提供了一种应用于锁相环（PLL）的压控振荡器（VCO）的频带选择方法及相关方法。 频带选择方法根据温度信号产生开环控制电压; 将开环控制电压输入到VCO中; 在VCO的多个频带之间顺序切换并产生用于频带的多个电压控制信号; 选择优选的电压控制信号及其对应的频带作为PLL的工作频带。

公开(公告)号：US07760844B2

公开(公告)日：2010-07-20

申请号：US12363792

申请日：2009-02-02

Applicant: Jian-Yu Ding ,  Shen-Ching Sun ,  Yao-Chi Wang ,  Chao-Tung Yang ,  Fucheng Wang ,  Shuo-Yuan Hsiao

Inventor： Jian-Yu Ding ,  Shen-Ching Sun ,  Yao-Chi Wang ,  Chao-Tung Yang ,  Fucheng Wang ,  Shuo-Yuan Hsiao

IPC: H03K21/00

CPC classification number: H03K23/584 ,  H03K23/665 ,  H03K23/667 ,  H03L7/193 ,  H03L7/1976

Abstract: A multi-modulus divider and a method for performing frequency dividing by utilizing a multi-modulus divider are disclosed. The multi-modulus divider comprises a multi-modulus dividing circuit, a pulse generating circuit, and a modulus signal generating circuit. The multi-modulus dividing circuit comprises several serially connected divider cells, of which a predetermined one may be bypassed. The multi-modulus dividing circuit generates an output frequency according to an input frequency and a divisor. A range of the divisor comprises a plurality of numerical intervals. The pulse generating circuit generates a pulse signal. The modulus signal generating circuit generates a determination result by determining which numerical interval the divisor belongs to, and inputs, according to the determination result, the pulse signal into the predetermined divider cell to be one of references which the predetermined divider cell refers to when outputting a modulus signal. The predetermined divider cell corresponds to the determination result.

Abstract translation: 公开了一种使用多模式分频器进行分频的多模式分频器和方法。 多模式分配器包括多模式分频电路，脉冲发生电路和模数信号发生电路。 多模式分频电路包括几个串联的分频器单元，其中预定的分频器可以被旁路。 多模式分频电路根据输入频率和除数产生输出频率。 除数的范围包括多个数字间隔。 脉冲发生电路产生脉冲信号。 模数信号发生电路通过确定除数属于哪个数值间隔来产生确定结果，并且根据确定结果将预定分频器单元中的脉冲信号输入为当输出时预定分频单元参考的参考之一 模数信号。 预定的分频器单元对应于确定结果。

公开(公告)号：US09071255B2

公开(公告)日：2015-06-30

申请号：US13609749

申请日：2012-09-11

Applicant: Cheng-Chieh Lin ,  Jian-Yu Ding ,  Yao-Chi Wang

Inventor： Cheng-Chieh Lin ,  Jian-Yu Ding ,  Yao-Chi Wang

IPC: H03L7/197 ,  H03L7/099 ,  H03L7/10

CPC classification number: H03L7/1976 ,  H03L7/099 ,  H03L7/104 ,  H03L2207/06

Abstract: A phase locked loop and an associated alignment method are provided. A disclosed phase locked loop receives a reference signal to provide a feedback signal. The phase locked loop is first opened. When the phase locked loop is open, a frequency range of an oscillating signal from a voltage-controlled oscillator is substantially selected. The feedback signal is provided according to the oscillation signal. After the frequency range is selected, the phase locked loop is kept open and the phases of the reference signal and the feedback signal are substantially aligned. The phase locked loop is then closed after the reference signal and the feedback signal are aligned.

Abstract translation: 提供了锁相环和相关对准方法。 所公开的锁相环接收参考信号以提供反馈信号。 首先打开锁相环。 当锁相环断开时，基本上选择来自压控振荡器的振荡信号的频率范围。 根据振荡信号提供反馈信号。 选择频率范围后，锁相环保持断开，参考信号和反馈信号的相位基本对齐。 然后在参考信号和反馈信号对齐后，闭锁环路。

公开(公告)号：US20130027111A1

公开(公告)日：2013-01-31

申请号：US13556392

申请日：2012-07-24

Applicant: YEN-TSO CHEN ,  Jian-Yu Ding

Inventor： YEN-TSO CHEN ,  Jian-Yu Ding

IPC: G06G7/16

CPC classification number: H03K23/662 ,  H03K23/667

Abstract: A multiple-modulus divider and an associated control method are provided. The multiple-modulus divider includes a divisor loader, a multiple-modulus dividing circuit and a modulus controller. The divisor loader downloads a divisor when a download signal indicates a start of a division period. The multiple-modulus circuit includes a plurality of cascaded divisors, and provides an output frequency according to an input frequency and the divisor. The dividers respectively output a plurality of modulus output signals, and each is operable under either a close-loop state or an open-loop state. The modulus controller selects and controls one of the dividers according to the divisor, and ensures the selected divider is maintained at the open-loop state when the division period ends. The download signal corresponds to one of the modulus output signals.

Abstract translation: 提供了多模式分频器和相关的控制方法。 多模式分配器包括除数加载器，多模式分割电路和模数控制器。 当下载信号指示分割期间的开始时，除数加载器下载除数。 多模电路包括多个级联除数，并根据输入频率和除数提供输出频率。 分频器分别输出多个模数输出信号，并且每个可在闭环状态或开环状态下操作。 模数控制器根据除数选择和控制一个分频器，并且在分频周期结束时确保所选择的分频器保持在开环状态。 下载信号对应于模数输出信号之一。