公开(公告)号：US6166582A

公开(公告)日：2000-12-26

申请号：US189439

申请日：1998-11-10

申请人： Jiunn-Chin Tseng ,  Howard Clayton Kirsch

发明人： Jiunn-Chin Tseng ,  Howard Clayton Kirsch

IPC分类号： H03K19/003 ,  H03K5/12 ,  H03K17/16

CPC分类号： H03K19/00361

摘要： A method and apparatus of an output buffer for controlling the ground bounce and power supply noise during output switching is provided. A CMOS output buffer comprises a P-channel output transistor, a N-channel output transistor and a predrive circuit. During output pull-down transition, the predrive circuit generates a first gate voltage on the pull-down N-channel output transistor for a predetermined time, and further generates a second voltage value which is smaller than the first voltage value, then returns to the first voltage value after the elapse of the predetermined time. The predrive circuit makes the pull-down N-channel output transistor stay in the saturation region longer than the uncontrolled scheme, the steep rising gate voltage on the N-channel output transistor can be avoided with a very little speed degradation but instead of better ground bounce improvement. During output pull-up transition, the predrive circuit generates a first gate voltage on the pull-up P-channel output transistor for a predetermined time, and further generates a second voltage which is higher than the first voltage value, then returns back to the first voltage value after the elapse of the predetermined time.

摘要翻译： 提供了一种用于在输出切换期间控制地面反弹和电源噪声的输出缓冲器的方法和装置。 CMOS输出缓冲器包括P沟道输出晶体管，N沟道输出晶体管和预驱动电路。 在输出下拉转换期间，预驱动电路在下拉N沟道输出晶体管上产生预定时间的第一栅极电压，并进一步产生小于第一电压值的第二电压值，然后返回到 经过预定时间后的第一电压值。 预驱动电路使下拉通道N沟道输出晶体管保持在比不受控制的方案更长的饱和区域中，可以以非常小的速度降低来避免N沟道输出晶体管上的陡峭的上升栅极电压，而不是更好的接地 反弹改善。 在输出上拉转换期间，预驱动电路在上拉P沟道输出晶体管上产生预定时间的第一栅极电压，并进一步产生高于第一电压值的第二电压，然后返回到 经过预定时间后的第一电压值。

公开(公告)号：US5949726A

公开(公告)日：1999-09-07

申请号：US120360

申请日：1998-07-22

申请人： Jiunn-Chin Tseng ,  Hon Shing Lau

发明人： Jiunn-Chin Tseng ,  Hon Shing Lau

IPC分类号： G11C29/50 ,  G11C7/00

CPC分类号： G11C29/50

摘要： This invention describes a biasing scheme that reduces burn-in testing time as well as the number of cycles through the burn-in test for a semiconductor memory. The magnitude of a substrate back bias is reduced when a semiconductor memory device is taken into burn-in at a first value of an external applied voltage. When the memory device is brought out of burn-in, the substrate back bias is returned to the original operating level at a second value of the external applied voltage. The reduction of the substrate back bias allows for a higher external voltage to stress the semiconductor memory without forcing breakdown and results in a shorter test time. The burn-in test is entered at a higher magnitude of the external applied voltage than the voltage at which burn-in testing is exited. This helps to reduce the number of cycles through the burn-in test by providing a stronger external bias.

摘要翻译： 本发明描述了通过半导体存储器的老化测试来减少老化测试时间以及循环次数的偏置方案。 当以外部施加电压的第一值将半导体存储器件置于老化状态时，衬底反向偏压的幅度减小。 当存储器件脱离老化时，衬底反向偏压以外部施加电压的第二值返回到初始工作电平。 衬底反向偏置的减小允许更高的外部电压对半导体存储器施加压力，而不会强制击穿并导致较短的测试时间。 老化测试在外部施加电压的大幅度下进入，而不是进行老化测试的电压。 这有助于通过提供更强的外部偏压来减少老化测试的周期数。