摘要:
This invention describes a biasing scheme that reduces burn-in testing time as well as the number of cycles through the burn-in test for a semiconductor memory. The magnitude of a substrate back bias is reduced when a semiconductor memory device is taken into burn-in at a first value of an external applied voltage. When the memory device is brought out of burn-in, the substrate back bias is returned to the original operating level at a second value of the external applied voltage. The reduction of the substrate back bias allows for a higher external voltage to stress the semiconductor memory without forcing breakdown and results in a shorter test time. The burn-in test is entered at a higher magnitude of the external applied voltage than the voltage at which burn-in testing is exited. This helps to reduce the number of cycles through the burn-in test by providing a stronger external bias.
摘要:
In some embodiments, a logic circuit is provided that has a plurality of gates with gate inputs. Also provided is one or more latch circuits coupled to the logic circuit to provide operational data when in an operational mode and to cause at least some of the gate inputs to be at values resulting in reduced leakage during a sleep mode. Additionally provided are embodiments of non-destructive latch circuits, which may be used to implement the latch circuits just discussed. Other embodiments are disclosed and/or claimed herein.
摘要:
An optoelectronic apparatus is described herein, including a transmitter, a receiver, and an optical waveguide, all of which are embedded in a PCB. The transmitter includes a laser generator and other circuits for generating electrical and optical signals, which are transmitted through the waveguide to the receiver. The receiver includes circuits and detectors for detecting and converting the optical signals to electrical signals. The circuit and optical components of the transmitter and receiver are integrated in 3D hybrid chip sets where the chip components are stacked in a 3D structure. Because all of the circuit and optical components are embedded in the PCB, the apparatus is made very compact and suitable for implementation in portable products.
摘要:
In some embodiments, a logic circuit is provided that has a plurality of gates with gate inputs. Also provided is one or more latch circuits coupled to the logic circuit to provide operational data when in an operational mode and to cause at least some of the gate inputs to be at values resulting in reduced leakage during a sleep mode. Additionally provided are embodiments of non-destructive latch circuits, which may be used to implement the latch circuits just discussed. Other embodiments are disclosed and/or claimed herein.
摘要:
In some embodiments, a logic circuit is provided that has a plurality of gates with gate inputs. Also provided is one or more latch circuits coupled to the logic circuit to provide operational data when in an operational mode and to cause at least some of the gate inputs to be at values resulting in reduced leakage during a sleep mode. Additionally provided are embodiments of non-destructive latch circuits, which may be used to implement the latch circuits just discussed. Other embodiments are disclosed and/or claimed herein.
摘要:
An optoelectronic apparatus is described herein, including a transmitter, a receiver, and an optical waveguide, all of which are embedded in a PCB. The transmitter includes a laser generator and other circuits for generating electrical and optical signals, which are transmitted through the waveguide to the receiver. The receiver includes circuits and detectors for detecting and converting the optical signals to electrical signals. The circuit and optical components of the transmitter and receiver are integrated in 3D hybrid chip sets where the chip components are stacked in a 3D structure. Because all of the circuit and optical components are embedded in the PCB, the apparatus is made very compact and suitable for implementation in portable products.
摘要:
In one embodiment, the present invention includes a method for receiving first and second data operands in a common execution unit and manipulating the operands responsive to an instruction to generate an output according to local control signals of a local controller of the execution unit. Various instruction types such as shuffle and shift operations may be performed in the common execution unit in a single cycle. Other embodiments are described and claimed.
摘要:
In some embodiments, a logic circuit is provided that has a plurality of gates with gate inputs. Also provided is one or more latch circuits coupled to the logic circuit to provide operational data when in an operational mode and to cause at least some of the gate inputs to be at values resulting in reduced leakage during a sleep mode. Additionally provided are embodiments of non-destructive latch circuits, which may be used to implement the latch circuits just discussed. Other embodiments are disclosed and/or claimed herein.
摘要:
In some embodiments, a logic circuit is provided that has a plurality of gates with gate inputs. Also provided is one or more latch circuits coupled to the logic circuit to provide operational data when in an operational mode and to cause at least some of the gate inputs to be at values resulting in reduced leakage during a sleep mode. Additionally provided are embodiments of non-destructive latch circuits, which may be used to implement the latch circuits just discussed. Other embodiments are disclosed and/or claimed herein.
摘要:
In one embodiment, the present invention includes a method for receiving first and second data operands in a common execution unit and manipulating the operands responsive to an instruction to generate an output according to local control signals of a local controller of the execution unit. Various instruction types such as shuffle and shift operations may be performed in the common execution unit in a single cycle. Other embodiments are described and claimed.