公开(公告)号：US20070183549A1

公开(公告)日：2007-08-09

申请号：US11349874

申请日：2006-02-08

申请人： John Angello ,  Satyavathi Akella ,  Kiyoshi Kase ,  May Len

发明人： John Angello ,  Satyavathi Akella ,  Kiyoshi Kase ,  May Len

IPC分类号： H04L25/38

CPC分类号： H04L25/38 ,  H04L7/0008

摘要： An adaptive variable length pulse synchronizer including a state keeper circuit, an asynchronous pulse edge detection circuit, a data synchronization circuit, and a pulse edge synchronization circuit. The state keeper circuit detects a leading edge of the asynchronous pulse. The asynchronous pulse edge detection circuit detects a trailing edge of the asynchronous pulse after the state keeper circuit has detected the leading edge. The asynchronous pulse edge detection circuit further provides a pulse synchronized with a clock signal after the asynchronous pulse has been detected. The data synchronization circuit latches the asynchronous data and provides the synchronous data in response to the synchronous pulse. The pulse edge synchronization provides the synchronous ready signal after synchronous data has been provided. In one embodiment, the synchronous pulse occurs between successive rising edges of the clock whereas the synchronous ready signal is provided in response to the intermediate falling edge of the clock.

摘要翻译： 一种自适应可变长度脉冲同步器，包括状态保持器电路，异步脉冲沿检测电路，数据同步电路和脉冲沿同步电路。 状态保持电路检测异步脉冲的前沿。 在状态保持电路检测到前沿之后，异步脉冲沿检测电路检测异步脉冲的后沿。 在检测到异步脉冲之后，异步脉冲沿检测电路还提供与时钟信号同步的脉冲。 数据同步电路锁存异步数据，并响应于同步脉冲提供同步数据。 在提供同步数据之后，脉冲沿同步提供同步就绪信号。 在一个实施例中，同步脉冲发生在时钟的连续上升沿之间，而响应于时钟的中间下降沿提供同步就绪信号。