公开(公告)号：US4809218A

公开(公告)日：1989-02-28

申请号：US823801

申请日：1986-01-29

申请人： Paul J. Natusch ,  David C. Senerchia ,  John F. Henry, Jr. deceased

发明人： Paul J. Natusch ,  David C. Senerchia ,  John F. Henry, Jr. deceased

IPC分类号： G06F13/16 ,  G06F13/28 ,  G06F13/36 ,  G06F12/02

CPC分类号： G06F13/28 ,  G06F13/16

摘要： In a data processing system having a multiple write command and a masked write command, a plurality of signal groups can be transferred from a data processing subsystem to a memory unit on consecutive system cycles. Associated with each signal group and applied to lines used to transfer mask signals are control signals that designate when the associated signal group is to stored in the memory unit. When the multiple write command is issued, the apparatus coupled to the mask signal lines is enabled and the control signals can be identified. When the control signals are identified, the operation storing the associated signal group is inhibited.

摘要翻译： 在具有多重写入命令和掩蔽写入命令的数据处理系统中，可以在连续的系统周期上将多个信号组从数据处理子系统传送到存储器单元。 与每个信号组相关并且应用于用于传送掩模信号的线路的控制信号是指定何时将相关信号组存储在存储器单元中的控制信号。 当发出多重写入命令时，启用耦合到掩模信号线的装置，并且可以识别控制信号。 当识别出控制信号时，禁止存储相关信号组的操作。

公开(公告)号：US4791552A

公开(公告)日：1988-12-13

申请号：US823951

申请日：1986-01-29

申请人： Paul J. Natusch ,  David C. Senerchia ,  John F. Henry, Jr., deceased

发明人： Paul J. Natusch ,  David C. Senerchia ,  John F. Henry, Jr., deceased

IPC分类号： G06F12/06 ,  G11C8/18 ,  G06F12/00

CPC分类号： G06F12/0607 ,  G11C8/18

摘要： Apparatus is disclosed for selecting a group of address signals to be applied to a memory unit array and for applying the address signals to the memory unit array to permit the activity associated with the address signals to be completed. The apparatus generates a multiplicity of signals controlling a latch-type buffer storage unit. The first generated signal insures that the signal controlling the buffer storage unit is active during application of the address signals to the system bus. The second generated signal overlaps the first generated signal and extends the signal controlling the buffer storage unit a small amount. The third generated signal overlaps the second generated signal and extends the signal controlling the buffer storage unit for the period of time necessary to utilize the memory unit array.

摘要翻译： 公开了用于选择要应用于存储器单元阵列的一组地址信号并将地址信号施加到存储器单元阵列以允许与地址信号相关联的活动完成的装置。 该装置产生控制锁存型缓冲存储单元的多个信号。 第一个产生的信号确保在将地址信号应用于系统总线时控制缓冲存储单元的信号有效。 第二产生的信号与第一生成信号重叠，并且将控制缓冲存储单元的信号扩展到少量。 第三产生的信号与第二个产生的信号重叠，并扩展控制缓冲存储单元的信号达到利用存储单元阵列所需的时间。

公开(公告)号：US07577640B1

公开(公告)日：2009-08-18

申请号：US10830288

申请日：2004-04-21

申请人： M. Alan Bland ,  John F. Henry ,  Danny Lee Prentice ,  Richard Shaffer Youngkin

发明人： M. Alan Bland ,  John F. Henry ,  Danny Lee Prentice ,  Richard Shaffer Youngkin

IPC分类号： G06F7/00 ,  G06F17/30

CPC分类号： G06F17/30575 ,  Y10S707/99933

摘要： A database architecture providing high availability and scalability is provided. According to embodiments of the present invention, multiple data sources are supported by multiple source databases. Partial copies of data stored in one or more of the source databases are provided to a consolidated database in response to requests for data received by the consolidated database from a data client. Multiple consolidated databases may support multiple data clients and data clients that are geographically dispersed. A sparse replication component operates to retrieve data from the source databases for storage in consolidated databases. The sparse data replication component can also monitor source databases for updates to requested data, and retrieve such data for storage in a consolidated database. In addition, each consolidated database may be associated with a data rationalization component to ensure that the data stored in the associated consolidated database does not include pathological data redundancies.

摘要翻译： 提供了提供高可用性和可扩展性的数据库架构。 根据本发明的实施例，多个数据源由多个源数据库支持。 存储在一个或多个源数据库中的数据的部分副本被提供给统一数据库，以响应来自数据客户端的由统一数据库接收的数据的请求。 多个统一数据库可能支持地理上分散的多个数据客户端和数据客户端。 稀疏复制组件用于从源数据库检索数据，以便在统一数据库中进行存储。 稀疏数据复制组件还可以监视源数据库以获取所请求数据的更新，并检索此类数据以便在统一数据库中进行存储。 此外，每个统一数据库可以与数据合理化组件相关联，以确保存储在相关统一数据库中的数据不包括病理数据冗余。

公开(公告)号：US4954946A

公开(公告)日：1990-09-04

申请号：US453088

申请日：1989-12-21

申请人： Paul J. Natusch ,  Eugene L. Yu ,  David C. Senerchia ,  John F. Henry, Jr., deceased

发明人： Paul J. Natusch ,  Eugene L. Yu ,  David C. Senerchia ,  John F. Henry, Jr., deceased

IPC分类号： G06F13/16 ,  G06F13/00

CPC分类号： G06F13/1615

摘要： For use in a data processing system, a main memory subsystem includes a plurality of memory boards for storing groups of logic signals. Each memory board includes an plurality of array units. Each array unit is adapted to store a group of logic signals that is equivalent in size to the field of data logic signals transferred on the system bus and has an address structure so that each addressable data signal group can be stored in a single array. The address field of each array unit is further adapted so that the probability of interfering activity in each array is low. The arrays are adapted process data signal groups independently, thus, activity involving several arrays can take place simultaneously. The memory subsystem is structured to provide a pipeline types of overlapping activity so that activity involving several array units can be in progress simultaneously. Because the manipulation of the storage cells requires the most amounts of time in the memory unit, and because the arrays are performing this activity independently for each signal group, then the memory unit can be adapted to process the signal groups applied sequentially to the system without delay in nonexceptional circumstances, the most general exceptional circumstance being the masked write operation.

摘要翻译： 为了在数据处理系统中使用，主存储器子系统包括用于存储逻辑信号组的多个存储器板。 每个存储器板包括多个阵列单元。 每个阵列单元适于存储一组逻辑信号，其大小与在系统总线上传送的数据逻辑信号的字段相当，并且具有地址结构，使得每个可寻址数据信号组可以存储在单个阵列中。 每个阵列单元的地址字段进一步被适配，使得每个阵列中的干扰活动的概率很低。 阵列是独立的适应过程数据信号组，因此，可以同时进行涉及几个阵列的活动。 存储器子系统被构造为提供重叠活动的流水线类型，使得涉及若干阵列单元的活动可以同时进行。 由于存储单元的操作需要在存储器单元中大量的时间，并且由于阵列对于每个信号组独立地执行该活动，因此存储器单元可以适于处理顺序地施加到系统的信号组而无需 在非感知情况下的延迟，最常见的例外情况是屏蔽写操作。