公开(公告)号：US06223142B1

公开(公告)日：2001-04-24

申请号：US09190861

申请日：1998-11-09

申请人： John Fowler Bargh ,  Wolfgang Roesner ,  Derek Edward Williams ,  Bryan R. Hunt

发明人： John Fowler Bargh ,  Wolfgang Roesner ,  Derek Edward Williams ,  Bryan R. Hunt

IPC分类号： G06F1750

CPC分类号： G06F17/5022

摘要： A method and system are disclosed that utilize the expressiveness of hardware description languages for incrementally compiling instrumentation logic into a simulation model of a digital circuit design. According to the present invention, a simulation model that includes a design entity file of a digital circuit design is generated. Next, an instrumentation entity file is associated with the design entity file, thereby producing an instrumented design entity file. Finally, and during the process of compiling the simulation model, for the instrumented design entity file: searching for a consistent and previously compiled version of said instrumented design entity file. In response to finding a consistent and previously compiled version, loading the consistent and previously compiled version into the simulation model. In response to finding no consistent and previously compiled version, loading and compiling the instrumented design entity file.

摘要翻译： 公开了一种利用硬件描述语言的表现力来逐步编译仪表逻辑到数字电路设计的仿真模型中的方法和系统。 根据本发明，生成包括数字电路设计的设计实体文件的仿真模型。 接下来，仪器实体文件与设计实体文件相关联，从而生成一个被检测的设计实体文件。 最后，在编译仿真模型的过程中，对于仪表化设计实体文件：搜索一致和先前编译的所述仪表化设计实体文件的版本。 为了找到一致和先前编译的版本，将一致和先前编译的版本加载到仿真模型中。 响应于找不到一致和先前编译的版本，加载和编译仪表化的设计实体文件。

公开(公告)号：US06470478B1

公开(公告)日：2002-10-22

申请号：US09345163

申请日：1999-06-29

申请人： John Fowler Bargh ,  Wolfgang Roesner ,  Derek Edward Williams

发明人： John Fowler Bargh ,  Wolfgang Roesner ,  Derek Edward Williams

IPC分类号： G06F1750

CPC分类号： G01R31/318357 ,  G01R31/31704 ,  G06F17/5022

摘要： A method and system that utilize the expressiveness of hardware description languages for efficiently and comprehensively monitoring performance characteristics of a digital circuit design during simulation. According to the present invention, a design entity that is part of a digital circuit design is first described utilizing a hardware description language. Next, a counting instrument is described utilizing the same hardware description language. The counting instrument is designed to detect occurrences of a count event within the design entity during simulation of the digital circuit design. The counting instrument is associated with the design entity utilizing a non-conventional call, such that the counting instrument may be utilized to monitor each instantiation of the design entity within the simulation model without the instrumentation entity becoming incorporated into the digital circuit design. In association with the counting instrument, a linear feedback shift register is automatically generated for recording the number of occurrences of the count event within the design entity.

摘要翻译： 一种利用硬件描述语言表达的方法和系统，用于在模拟期间高效全面地监测数字电路设计的性能特征。 根据本发明，首先使用硬件描述语言描述作为数字电路设计的一部分的设计实体。 接下来，使用相同的硬件描述语言来描述计数仪器。 计数仪器被设计为在模拟数字电路设计期间检测设计实体内的计数事件的发生。 计数仪器与设计实体相关联，利用非传统调用，使得计数仪器可用于监视模拟模型内的设计实体的每个实例化，而不需要将仪器实体纳入数字电路设计。 与计数仪器相关联，自动生成线性反馈移位寄存器，用于记录设计实体内计数事件的发生次数。

公开(公告)号：US06212491B1

公开(公告)日：2001-04-03

申请号：US09190862

申请日：1998-11-09

申请人： John Fowler Bargh ,  Bryan Ronald Hunt ,  Wolfgang Roesner ,  Derek Edward Williams

发明人： John Fowler Bargh ,  Bryan Ronald Hunt ,  Wolfgang Roesner ,  Derek Edward Williams

IPC分类号： G06F1750

CPC分类号： G06F17/5022

摘要： A method and system are disclosed that utilize the expressiveness of hardware description languages for automatically adjusting counting rates of instrumentation within a simulation model of a digital circuit design, during simulation of said digital circuit design. According to the present invention a design entity that will be incorporated into a simulation model of a digital circuit design is described utilizing a hardware description language. The design entity operates, during simulation, in conformity with a design cycle that consists of a multiple of a simulator cycle. Next, an instrumentation entity is described utilizing the same hardware description language. The description of the instrumentation entity contains logic to detect occurrences of a count event that occurs in conformity with the design cycle during simulation. Thereafter, an instrumentation logic block associated with the instrumentation entity is automatically generated and utilized for counting occurrences of the count event detected by the instrumentation entity. Finally, the design cycle is encoded within the instrumentation entity, such that the output logic block is automatically adjusted to count in conformity with the design cycle.

摘要翻译： 公开了一种在所述数字电路设计的仿真期间利用硬件描述语言的表现性来自动调整数字电路设计的仿真模型中的仪表的计数率的方法和系统。 根据本发明，将使用硬件描述语言描述将被并入数字电路设计的仿真模型中的设计实体。 设计实体在模拟期间运行，符合由模拟器周期的倍数组成的设计周期。 接下来，使用相同的硬件描述语言来描述仪器实体。 仪表实体的描述包含检测在仿真期间符合设计周期发生的计数事件发生的逻辑。 此后，与仪器实体相关联的仪表逻辑块被自动生成并用于计数由仪器实体检测到的计数事件的发生。 最后，设计周期在仪器实体内进行编码，使输出逻辑块自动调整为符合设计周期。

公开(公告)号：US06202042B1

公开(公告)日：2001-03-13

申请号：US09190863

申请日：1998-11-09

申请人： John Fowler Bargh ,  Bryan Ronald Hunt ,  Wolfgang Roesner ,  Derek Edward Williams

发明人： John Fowler Bargh ,  Bryan Ronald Hunt ,  Wolfgang Roesner ,  Derek Edward Williams

IPC分类号： G06F1750

CPC分类号： G06F17/5022

摘要： A method and system are disclosed that utilize the expressiveness of hardware description languages for providing comprehensive runtime monitoring during hardware accelerated simulation of a digital circuit design. According to the present invention a design entity forming part of a digital circuit design that will be translated and assembled into a simulation executable model, is described utilizing a hardware description language. Next, an instrumentation entity designed to send a failure signal in response to detecting an occurrence of a failure event within the simulation executable model is described utilizing the same hardware description language. Thereafter, a simulation test is initiated on the simulation executable model utilizing a hardware simulator. Finally, during the simulation test, and in response to receiving a failure signal from the instrumentation entity, the simulation test is terminated such that the failure event may be efficiently identified and diagnosed.

摘要翻译： 公开了一种方法和系统，其利用硬件描述语言的表现性来在数字电路设计的硬件加速仿真期间提供全面的运行时监视。 根据本发明，利用硬件描述语言描述形成将被翻译并组装成模拟可执行模型的数字电路设计的一部分的设计实体。 接下来，使用相同的硬件描述语言来描述被设计成响应于检测模拟可执行模型内的故障事件的发生而发送故障信号的仪表实体。 此后，利用硬件模拟器对仿真可执行模型进行模拟测试。 最后，在仿真测试期间，并且响应于接收到来自仪器实体的故障信号，模拟测试被终止，从而可以有效地识别和诊断故障事件。

公开(公告)号：US06195629B1

公开(公告)日：2001-02-27

申请号：US09190864

申请日：1998-11-09

申请人： John Fowler Bargh ,  Bryan Ronald Hunt ,  Wolfgang Roesner ,  Derek Edward Williams

发明人： John Fowler Bargh ,  Bryan Ronald Hunt ,  Wolfgang Roesner ,  Derek Edward Williams

IPC分类号： G06F1750

CPC分类号： G06F17/5022

摘要： A method and system are disclosed that utilize the expressiveness of hardware description languages for selectively disabling instrumentation during simulation of a digital circuit design. According to the present invention, an instrumentation entity, described utilizing a hardware description language to include an output signal to indicate an occurrence of an event during simulation, is implemented into a simulation model of a digital circuit design. Next, the output signal is associated with a unique output storage element. Finally, a disable mechanism uniquely associated with said output signal is provided, such that the output signal may be selectively masked by disabling the storage element during simulation testing of the digital circuit design.

摘要翻译： 公开了一种在数字电路设计仿真期间利用硬件描述语言的表现力来选择性地禁用仪器的方法和系统。 根据本发明，利用硬件描述语言描述的包括用于指示模拟期间的事件发生的输出信号的仪表实体被实现为数字电路设计的仿真模型。 接下来，输出信号与唯一的输出存储元件相关联。 最后，提供与所述输出信号唯一相关联的禁用机制，使得可以通过在数字电路设计的模拟测试期间禁用存储元件来选择性地屏蔽输出信号。

公开(公告)号：US06195627B1

公开(公告)日：2001-02-27

申请号：US09190865

申请日：1998-11-09

申请人： John Fowler Bargh ,  Bryan Ronald Hunt ,  Wolfgang Roesner ,  Derek Edward Williams

发明人： John Fowler Bargh ,  Bryan Ronald Hunt ,  Wolfgang Roesner ,  Derek Edward Williams

IPC分类号： G06F1750

CPC分类号： G06F17/5022

摘要： A method and system are disclosed that utilize the expressiveness of hardware description languages for efficiently and comprehensively monitoring performance characteristics of a digital circuit design during simulation. According to the present invention, a design entity that is part of a digital circuit design is first described utilizing a hardware description language. Next, an instrumentation entity is described utilizing the same hardware description language. Thereafter, the design entity is instantiated in at least one instance within a simulation model of a digital circuit design. Finally, the instrumentation entity is associated with the design entity utilizing a non-conventional call, such that the instrumentation entity may be utilized to monitor each instantiation of the design entity within the simulation model without the instrumentation entity becoming incorporated into the digital circuit design.

摘要翻译： 公开了利用硬件描述语言的表达性来有效且全面地监测模拟期间数字电路设计的性能特征的方法和系统。 根据本发明，首先使用硬件描述语言描述作为数字电路设计的一部分的设计实体。 接下来，使用相同的硬件描述语言来描述仪器实体。 此后，设计实体在数字电路设计的仿真模型内的至少一个实例中实例化。 最后，仪器实体利用非常规呼叫与设计实体相关联，使得仪表实体可以用于监视模拟模型内的设计实体的每个实例化，而没有将仪器实体并入数字电路设计。