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公开(公告)号：US06212491B1
公开(公告)日：2001-04-03
申请号：US09190862
申请日：1998-11-09
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A method and system are disclosed that utilize the expressiveness of hardware description languages for automatically adjusting counting rates of instrumentation within a simulation model of a digital circuit design, during simulation of said digital circuit design. According to the present invention a design entity that will be incorporated into a simulation model of a digital circuit design is described utilizing a hardware description language. The design entity operates, during simulation, in conformity with a design cycle that consists of a multiple of a simulator cycle. Next, an instrumentation entity is described utilizing the same hardware description language. The description of the instrumentation entity contains logic to detect occurrences of a count event that occurs in conformity with the design cycle during simulation. Thereafter, an instrumentation logic block associated with the instrumentation entity is automatically generated and utilized for counting occurrences of the count event detected by the instrumentation entity. Finally, the design cycle is encoded within the instrumentation entity, such that the output logic block is automatically adjusted to count in conformity with the design cycle.
摘要翻译： 公开了一种在所述数字电路设计的仿真期间利用硬件描述语言的表现性来自动调整数字电路设计的仿真模型中的仪表的计数率的方法和系统。 根据本发明，将使用硬件描述语言描述将被并入数字电路设计的仿真模型中的设计实体。 设计实体在模拟期间运行，符合由模拟器周期的倍数组成的设计周期。 接下来，使用相同的硬件描述语言来描述仪器实体。 仪表实体的描述包含检测在仿真期间符合设计周期发生的计数事件发生的逻辑。 此后，与仪器实体相关联的仪表逻辑块被自动生成并用于计数由仪器实体检测到的计数事件的发生。 最后，设计周期在仪器实体内进行编码，使输出逻辑块自动调整为符合设计周期。
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公开(公告)号：US06202042B1
公开(公告)日：2001-03-13
申请号：US09190863
申请日：1998-11-09
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A method and system are disclosed that utilize the expressiveness of hardware description languages for providing comprehensive runtime monitoring during hardware accelerated simulation of a digital circuit design. According to the present invention a design entity forming part of a digital circuit design that will be translated and assembled into a simulation executable model, is described utilizing a hardware description language. Next, an instrumentation entity designed to send a failure signal in response to detecting an occurrence of a failure event within the simulation executable model is described utilizing the same hardware description language. Thereafter, a simulation test is initiated on the simulation executable model utilizing a hardware simulator. Finally, during the simulation test, and in response to receiving a failure signal from the instrumentation entity, the simulation test is terminated such that the failure event may be efficiently identified and diagnosed.
摘要翻译： 公开了一种方法和系统，其利用硬件描述语言的表现性来在数字电路设计的硬件加速仿真期间提供全面的运行时监视。 根据本发明，利用硬件描述语言描述形成将被翻译并组装成模拟可执行模型的数字电路设计的一部分的设计实体。 接下来，使用相同的硬件描述语言来描述被设计成响应于检测模拟可执行模型内的故障事件的发生而发送故障信号的仪表实体。 此后，利用硬件模拟器对仿真可执行模型进行模拟测试。 最后，在仿真测试期间，并且响应于接收到来自仪器实体的故障信号，模拟测试被终止，从而可以有效地识别和诊断故障事件。
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3.发明授权公开(公告)号：US06195629B1
公开(公告)日：2001-02-27
申请号：US09190864
申请日：1998-11-09
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A method and system are disclosed that utilize the expressiveness of hardware description languages for selectively disabling instrumentation during simulation of a digital circuit design. According to the present invention, an instrumentation entity, described utilizing a hardware description language to include an output signal to indicate an occurrence of an event during simulation, is implemented into a simulation model of a digital circuit design. Next, the output signal is associated with a unique output storage element. Finally, a disable mechanism uniquely associated with said output signal is provided, such that the output signal may be selectively masked by disabling the storage element during simulation testing of the digital circuit design.
摘要翻译： 公开了一种在数字电路设计仿真期间利用硬件描述语言的表现力来选择性地禁用仪器的方法和系统。 根据本发明，利用硬件描述语言描述的包括用于指示模拟期间的事件发生的输出信号的仪表实体被实现为数字电路设计的仿真模型。 接下来，输出信号与唯一的输出存储元件相关联。 最后，提供与所述输出信号唯一相关联的禁用机制，使得可以通过在数字电路设计的模拟测试期间禁用存储元件来选择性地屏蔽输出信号。
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公开(公告)号：US06195627B1
公开(公告)日：2001-02-27
申请号：US09190865
申请日：1998-11-09
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A method and system are disclosed that utilize the expressiveness of hardware description languages for efficiently and comprehensively monitoring performance characteristics of a digital circuit design during simulation. According to the present invention, a design entity that is part of a digital circuit design is first described utilizing a hardware description language. Next, an instrumentation entity is described utilizing the same hardware description language. Thereafter, the design entity is instantiated in at least one instance within a simulation model of a digital circuit design. Finally, the instrumentation entity is associated with the design entity utilizing a non-conventional call, such that the instrumentation entity may be utilized to monitor each instantiation of the design entity within the simulation model without the instrumentation entity becoming incorporated into the digital circuit design.
摘要翻译： 公开了利用硬件描述语言的表达性来有效且全面地监测模拟期间数字电路设计的性能特征的方法和系统。 根据本发明，首先使用硬件描述语言描述作为数字电路设计的一部分的设计实体。 接下来，使用相同的硬件描述语言来描述仪器实体。 此后，设计实体在数字电路设计的仿真模型内的至少一个实例中实例化。 最后，仪器实体利用非常规呼叫与设计实体相关联，使得仪表实体可以用于监视模拟模型内的设计实体的每个实例化，而没有将仪器实体并入数字电路设计。
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公开(公告)号：US06978231B2
公开(公告)日：2005-12-20
申请号：US09729465
申请日：2000-12-05
CPC分类号： G06F8/43 , G06F17/5022 , G06F17/5045
摘要： A method and program product for instrumenting a hardware description language (HDL) design entity. The design entity is created utilizing a HDL source code file within the syntax convention of a platform HDL. In accordance with the method of the present invention an instrumentation entity is described within the HDL source code file utilizing a non-conventional syntax comment such that the instrumentation entity is embedded within the design entity without being incorporated into an overall design in which the design entity is incorporated. In accordance with a second embodiment, the HDL source code file includes a description of at least one operating event within the conventional syntax of the platform HDL, and the method of the present invention further includes associating the instrumentation entity with the operating event utilizing a non-conventional syntax comment within the HDL source code file.
摘要翻译： 一种用于测量硬件描述语言（HDL）设计实体的方法和程序产品。 使用平台HDL的语法约定中的HDL源代码文件来创建设计实体。 根据本发明的方法，使用非常规语法注释在HDL源代码文件内描述仪器实体，使得仪器实体嵌入在设计实体内，而不被并入整体设计中，其中设计实体 被纳入。 根据第二实施例，HDL源代码文件包括平台HDL的常规语法中的至少一个操作事件的描述，并且本发明的方法还包括：使用非标准语言来将检测实体与操作事件相关联， HDL源代码文件中的常规语法注释。
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6.发明授权Method, system and program product for utilizing a configuration database to configure a hardware digital system 有权用于利用配置数据库配置硬件数字系统的方法，系统和程序产品公开(公告)号：US06826732B2
公开(公告)日：2004-11-30
申请号：US10425075
申请日：2003-04-28
IPC分类号： G06F1750
CPC分类号： G06F17/5022 , G06F17/5045
摘要： A configuration database associated with a hardware system stores at least one data structure defining a Dial instance and a mapping between each of a plurality of possible input values of the Dial instance and a respective one of a corresponding plurality of output values, where the plurality of output values controls which of a plurality of different possible latch values is placed in a hardware latch to configure the hardware system. The configuration database further indicates an association between the Dial instance and the hardware latch. In response to receipt of a request specifying an input value for the Dial instance, the configuration database is accessed to determine an output value for the Dial instance based upon the mapping. In addition, a latch value is obtained based upon the output value and the association. The latch value is then provided to the hardware system to set the hardware latch to the desired latch value.
摘要翻译： 与硬件系统相关联的配置数据库存储定义Dial实例的至少一个数据结构以及Dial实例的多个可能的输入值中的每一个与相应的多个输出值中的相应的一个之间的映射，其中多个 输出值控制多个不同可能的锁存值中的哪一个被放置在硬件锁存器中以配置硬件系统。 配置数据库还指示Dial实例和硬件锁存器之间的关联。 响应于接收到指定Dial实例的输入值的请求，访问配置数据库以基于映射来确定Dial实例的输出值。 此外，基于输出值和关联来获得锁存值。 然后将锁存值提供给硬件系统，以将硬件锁存器设置为所需的锁存值。
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7.发明授权Method, system and program product for configuring a simulation model of a digital design 失效用于配置数字设计仿真模型的方法，系统和程序产品公开(公告)号：US07162404B2
公开(公告)日：2007-01-09
申请号：US10425041
申请日：2003-04-28
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5022
摘要： A configuration database associated with a digital design stores at least one data structure defining a Dial instance and a mapping between each possible input value of the Dial instance and a respective output value. The output value controls which of a number of different possible latch values is placed in a configuration latch to configure a functional portion of a simulation model of the digital design. The configuration database further indicates an association between the Dial instance and the configuration latch. In response to a request specifying an input value for the Dial instance, the data structure in the configuration database is accessed to determine an output value for the Dial instance based upon the mapping. In addition, a latch value for the configuration latch is obtained based upon the output value and the association indicated by the configuration database. The latch value is then utilized to set the configuration latch in the simulation model.
摘要翻译： 与数字设计相关联的配置数据库存储定义Dial实例的至少一个数据结构以及Dial实例的每个可能的输入值与相应的输出值之间的映射。 输出值控制将多个不同可能的锁存值中的哪一个放置在配置锁存器中以配置数字设计的仿真模型的功能部分。 配置数据库还指示Dial实例和配置锁存器之间的关联。 响应于指定Dial实例的输入值的请求，访问配置数据库中的数据结构，以基于映射确定Dial实例的输出值。 此外，基于由配置数据库指示的输出值和关联来获得配置锁存器的锁存值。 然后使用锁存值在仿真模型中设置配置锁存器。
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8.发明授权Method, system and program product for determining a configuration of a digital design by reference to an invertible configuration database 失效通过参考可逆配置数据库来确定数字设计的配置的方法，系统和程序产品公开(公告)号：US07266489B2
公开(公告)日：2007-09-04
申请号：US10425053
申请日：2003-04-28
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , Y10S707/99945 , Y10S707/99948
摘要： A method for determining the configuration of a digital design first obtains a set of latch values of a plurality of latches within the digital design. A setting of a Dial instance is then determined based upon the set of latch values by reference to a configuration database that specifies a mapping table uniquely associating each a plurality of different settings of the Dial with a respective one of a plurality of different sets of latch values. The setting of the Dial instance is then output. In one embodiment, the setting of the Dial is contained in a simulation setup file utilized to configure a simulation model to a state approximating the state of the digital design represented by the set of latch values.
摘要翻译： 用于确定数字设计的配置的方法首先获得数字设计内的多个锁存器的一组锁存值。 然后，通过参考配置数据库，基于锁定值的集合来确定Dial实例的设置，该配置数据库指定将Dial的多个不同设置中的每一个与多个不同组的锁存器中的相应一个独立地相关联的映射表 价值观。 然后输出拨号实例的设置。 在一个实施例中，Dial的设置包含在用于将仿真模型配置为接近由锁定值组表示的数字设计的状态的状态的模拟设置文件中。
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9.发明授权Method, system and program product for specifying a configuration of a digital system described by a hardware description language (HDL) model 失效用于指定由硬件描述语言（HDL）模型描述的数字系统的配置的方法，系统和程序产品公开(公告)号：US07080347B2
公开(公告)日：2006-07-18
申请号：US10425096
申请日：2003-04-28
CPC分类号： G06F17/5045
摘要： A method of specifying a configurable digital system is disclosed. According to the method, at least one design entity containing a functional portion of a digital system is specified in at least one hardware definition language (HDL) file. The design entity logically contains a configuration latch having a plurality of different possible configuration values that each corresponds to a different configuration of the functional portion of the digital system. A statement in the HDL file associates a Dial entity with the design entity. The Dial has a Dial input, a Dial output, and a mapping table indicating a mapping between each of a plurality of possible input values that can be received at the Dial input and a respective corresponding output value for the Dial output. The output value specifies which of the plurality of different possible configuration values is loaded into the configuration latch.
摘要翻译： 公开了一种指定可配置数字系统的方法。 根据该方法，在至少一个硬件定义语言（HDL）文件中指定包含数字系统的功能部分的至少一个设计实体。 设计实体逻辑地包含具有多个不同可能配置值的配置锁存器，每个配置值对应于数字系统的功能部分的不同配置。 HDL文件中的一个声明将Dial实体与设计实体相关联。 拨号具有拨号输入，拨号输出和映射表，其指示可以在拨号输入处接收的多个可能的输入值中的每一个与拨号输出的相应对应的输出值之间的映射。 输出值指定多个不同可能配置值中的哪一个加载到配置锁存器中。
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公开(公告)号：US20100262975A1
公开(公告)日：2010-10-14
申请号：US12422701
申请日：2009-04-13
申请人： John Richard Reysa , Bryan Ronald Hunt , Stephen McCants , Tierney Bruce McCaughrin , Brain Lee Kozitza
发明人： John Richard Reysa , Bryan Ronald Hunt , Stephen McCants , Tierney Bruce McCaughrin , Brain Lee Kozitza
IPC分类号： G06F9/50
CPC分类号： G06F9/5077 , G06F9/4843
摘要： A job submission method that presents a set of algorithms that provide automated workload selection to a batch processing system that has the ability to receive and run jobs on various computing resources simultaneously is provided. If all machines in the batch system are running jobs, a queue containing the extra jobs for execution results. For compute intensive workloads, such as chip design, an automated workload selection system software layer submits jobs to the batch processing system. This keeps the batch processing system continually full of useful work The job submission system provides for organizing workloads, assigning relative ratios between workloads, associating arbitrary workload validation algorithms with a workload or parent workload, associating arbitrary selection algorithms with a workload or workload group, defining high priority workloads that preserve fairness and balancing the workload selection based on current status of the batch system, validation status, and the workload ratios.
摘要翻译： 提供了一种作业提交方法，其提供了一组算法，其向具有在各种计算资源上接收和运行作业的能力的批处理系统提供自动工作负载选择。 如果批处理系统中的所有计算机均运行作业，则包含执行结果的额外作业的队列。 对于计算密集型工作负载（如芯片设计），自动工作负载选择系统软件层将作业提交给批处理系统。 这使得批处理系统不断充满有用的工作作业提交系统提供组织工作负载，分配工作负载之间的相对比例，将任意工作负载验证算法与工作负载或父工作负载相关联，将任意选择算法与工作负载组或工作负载组相关联，定义 高优先级工作负载，根据批处理系统的当前状态，验证状态和工作负载比保持公平性并平衡工作负载选择。
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