公开(公告)号：US5900021A

公开(公告)日：1999-05-04

申请号：US833105

申请日：1997-04-04

申请人： John William Tiede ,  Jon Allan Faue

发明人： John William Tiede ,  Jon Allan Faue

IPC分类号： G11C7/10 ,  H03K19/173 ,  G06F12/00 ,  G11C7/00

CPC分类号： H03K19/173 ,  G11C7/1045

摘要： A configurable input device for an integrated circuit having a plurality of input pads, the input device including a plurality of buffers, where each buffer is associated with one of the input pads. Each buffer receives a mode select signal and the buffer is responsive to the mode select signal to place the buffer in an enabled mode or a disabled mode. A receiver portion within each buffer is coupled to the associated input pad. The receiver portion pulls the associated input pad to a preselected logic state while the buffer is in the disabled mode. An output driver within each buffer generates an output signal responsive to a signal on the associated input pad while the buffer is in the enable mode and provides a high impedance while the buffer is in the disabled mode. An output node is coupled to the output drivers of the plurality of buffers.

摘要翻译： 一种用于具有多个输入焊盘的集成电路的可配置输入设备，所述输入设备包括多个缓冲器，其中每个缓冲器与所述输入焊盘中的一个相关联。 每个缓冲器接收模式选择信号，并且缓冲器响应于模式选择信号以将缓冲器置于启用模式或禁用模式。 每个缓冲器内的接收器部分耦合到相关联的输入焊盘。 当缓冲器处于禁用模式时，接收器部分将相关联的输入焊盘拉至预选逻辑状态。 每个缓冲器中的输出驱动器在缓冲器处于使能模式时响应于相关输入焊盘上的信号产生输出信号，并且在缓冲器处于禁用模式时提供高阻抗。 输出节点耦合到多个缓冲器的输出驱动器。

公开(公告)号：US5973980A

公开(公告)日：1999-10-26

申请号：US121253

申请日：1998-07-23

申请人： John William Tiede ,  Jon Allan Faue

发明人： John William Tiede ,  Jon Allan Faue

IPC分类号： G05F1/46 ,  G11C7/00

CPC分类号： G05F1/465

摘要： An on-chip voltage regulator for controlling a gate of a regulator transistor having a first terminal coupled to receive an external power supply voltage and a second terminal coupled to provide a regulated voltage level to an internal circuit formed on a chip on which the on-chip voltage regulator is formed. The on-chip voltage regulator includes circuitry for detecting when a high current load to which the second terminal of the regulator transistor is coupled is activated. A control transistor is provided having a first terminal coupled to receive the external power supply voltage, a second terminal coupled to the gate of the regulator transistor, and a gate responsive to the means for detecting. In operation, a control voltage with an overshoot portion having preselected duration is generated on the gate of the regulator transistor in response to the activation of the high current load.

摘要翻译： 一种用于控制具有耦合以接收外部电源电压的第一端子的稳压晶体管的栅极的片上电压调节器，以及耦合到对芯片上形成的内部电路提供调节的电压电平的第二端子， 形成片式稳压器。 片上电压调节器包括用于检测何时将稳压晶体管的第二端耦合到的高电流负载被激活的电路。 提供控制晶体管，其具有耦合以接收外部电源电压的第一端子，耦合到调节器晶体管的栅极的第二端子和响应于用于检测的装置的栅极。 在操作中，响应于高电流负载的激活，在调节晶体管的栅极上产生具有预选持续时间的过冲部分的控制电压。

公开(公告)号：US5818291A

公开(公告)日：1998-10-06

申请号：US833083

申请日：1997-04-04

申请人： John William Tiede ,  Jon Allan Faue

发明人： John William Tiede ,  Jon Allan Faue

IPC分类号： G05F1/46 ,  G05F1/10

CPC分类号： G05F1/465

摘要： An on-chip voltage regulator for controlling a gate of a regulator transistor having a first terminal coupled to receive an external power supply voltage and a second terminal coupled to provide a regulated voltage level to an internal circuit formed on a chip on which the on-chip voltage regulator is formed. The on-chip voltage regulator includes circuitry for detecting when a high current load to which the second terminal of the regulator transistor is coupled is activated. A control transistor is provided having a first terminal coupled to receive the external power supply voltage, a second terminal coupled to the gate of the regulator transistor, and a gate responsive to the means for detecting. In operation, a control voltage with an overshoot portion having preselected duration is generated on the gate of the regulator transistor in response to the activation of the high current load.