公开(公告)号：US06901546B2

公开(公告)日：2005-05-31

申请号：US09876753

申请日：2001-06-07

申请人： Sam Gat-Shang Chu ,  Joachim Gerhard Clabes ,  Michael Normand Goulet ,  Johnny J. Leblanc ,  James Douglas Warnock

发明人： Sam Gat-Shang Chu ,  Joachim Gerhard Clabes ,  Michael Normand Goulet ,  Johnny J. Leblanc ,  James Douglas Warnock

IPC分类号： G01R31/317 ,  G01R31/3185 ,  G01R31/3187 ,  G06F11/27 ,  G01R31/28 ,  G06R11/00

CPC分类号： G01R31/3187 ,  G01R31/31705 ,  G01R31/318502 ,  G06F11/27

摘要： A device for fault testing in a microprocessor chip provides a LBIST circuit which has a first reference signature. A loading unit is further provided for receiving and outputting a set of masking data. A file unit connected to the loading unit is yet further provided for receiving the masking data. A masking unit connected to the file unit is yet further provided for generating a second reference signature based on the masking data from the file unit and a scanning data from a scan string in the chip. And, a signature logic connected to the output of the masking unit is yet further provided for compressing the second reference signature and inputting the compressed second reference signature to the LBIST circuit, wherein the compressed second reference signature replaces the first reference signature.

摘要翻译： 用于微处理器芯片中的故障测试的装置提供具有第一参考标识的LBIST电路。 进一步提供加载单元，用于接收和输出一组屏蔽数据。 还提供连接到加载单元的文件单元用于接收掩蔽数据。 还提供连接到文件单元的掩蔽单元，用于基于来自文件单元的掩蔽数据和来自芯片中的扫描串的扫描数据来生成第二参考签名。 并且，还提供连接到屏蔽单元的输出的签名逻辑，用于压缩第二参考签名并将压缩的第二参考签名输入到LBIST电路，其中压缩的第二参考签名替换第一参考签名。

公开(公告)号：US20100179784A1

公开(公告)日：2010-07-15

申请号：US12354063

申请日：2009-01-15

申请人： Patrick R. Crosby ,  Daniel W. Cervantes ,  Johnny J. LeBlanc ,  Samuel I. Ward

发明人： Patrick R. Crosby ,  Daniel W. Cervantes ,  Johnny J. LeBlanc ,  Samuel I. Ward

IPC分类号： G01R31/00 ,  G01R31/02

CPC分类号： G01R31/318547

摘要： A method for test pattern compression generates a first test pattern comprising a plurality of bits. The method identifies bits comprising a don't-care bit value in the first test pattern and replaces the identified bit values with random bit values, to generate a second test pattern. The method determines a fault coverage level of the second test pattern. In the event the determined fault coverage level of the second test pattern exceeds a predetermined individual test pattern fault coverage level, for at least one bit position in the second test pattern corresponding to a replaced identified bit value and detecting at least one fault, the method exchanges the don't care value in the bit position in the first test pattern with the bit value in the corresponding bit position in the second test pattern. The method merges subsequent test patterns that increase fault coverage with the second test pattern.

摘要翻译： 测试图案压缩的方法产生包括多个位的第一测试图案。 该方法识别在第一测试模式中包含不关心位值的位，并且用随机位值替换所识别的位值，以产生第二测试模式。 该方法确定第二测试模式的故障覆盖水平。 在第二测试模式的所确定的故障覆盖水平超过预定的单独测试模式故障覆盖水平的情况下，对于与替换的所识别的位值相对应的第二测试模式中的至少一个位位置并检测至少一个故障，该方法 在第一测试模式中的位位置交换不关心值的第二测试模式中相应位位置的位值。 该方法将随后的测试模式合并，以增加第二个测试模式的故障覆盖。

公开(公告)号：US4852061A

公开(公告)日：1989-07-25

申请号：US313300

申请日：1989-02-21

申请人： Henry C. Baron ,  Johnny J. LeBlanc ,  Thomas M. Storey ,  Joseph W. Yoder

发明人： Henry C. Baron ,  Johnny J. LeBlanc ,  Thomas M. Storey ,  Joseph W. Yoder

IPC分类号： G11C7/10

CPC分类号： G11C7/106 ,  G11C7/1051 ,  G11C2207/108

摘要： The improved register file includes an array of storage cells arranged in columns and rows, each column having a pair of bit lines for writing into the cell. Each storage cell includes a flip-flop cell having a first storage node connected to a respective read line which is unique for that cell. A read address latch has an enabling input connected to the master clock signal which is the same master clock signal for the LSSD logic on the integrated circuit chip. The read address latch applies its decoded output to a multiplexer which selects those read lines coming from one of the rows of storage cells in the array, and applies those selected read lines to an output storage cell array. The output storage cell array is enabled by a slave clock signal which is the same slave clock signal employed in the LSSD logic on the same integrated circuit chip. The output storage cell array stores the data from the selected read lines out of the multiplexer. The multiplexer propagates the data signals output from the read lines and performs the selection during the delay period between the master clock signal and the slave clock signal. Thus, the circuit makes use of the dead time between the master clock signal and the slave clock signal which was heretofore wasted, in performing the selection of the read lines for latching in the output storage cell array. The feature of connecting separate read lines to each respective storage cell in the array allows the independent accessing of different register rows in the register file for reading and writing, during the same logic cycle defined by the interval for the occurrence of both the master and the slave clock pulses.

摘要翻译： 改进的寄存器文件包括以列和行排列的存储单元的阵列，每列具有用于写入单元的一对位线。 每个存储单元包括触发器单元，其具有连接到该单元的唯一的相应读取线的第一存储节点。 读地址锁存器具有连接到主时钟信号的使能输入，该主时钟信号与集成电路芯片上的LSSD逻辑相同的主时钟信号。 读地址锁存器将其解码的输出应用于多路复用器，该多路复用器选择来自阵列中的一行存储单元的读取线，并将这些所选择的读取行应用于输出存储单元阵列。 输出存储单元阵列由在同一集成电路芯片上的LSSD逻辑中使用的从时钟信号相同的从时钟信号使能。 输出存储单元阵列将来自所选读取线的数据存储在多路复用器中。 多路复用器传播从读线输出的数据信号，并在主时钟信号和从时钟信号之间的延迟周期内进行选择。 因此，在执行选择用于锁定在输出存储单元阵列中的读取线的情况下，电路利用原始时钟信号和从时钟信号之间的死区时间。 将单独的读取线连接到阵列中的每个相应的存储单元的特征允许在寄存器文件中的不同寄存器行的独立访问以在由主器件和发生器的发生的间隔定义的相同逻辑周期期间进行读取和写入 从时钟脉冲。

公开(公告)号：US06539491B1

公开(公告)日：2003-03-25

申请号：US09436111

申请日：1999-11-08

申请人： Timothy M. Skergan ,  Johnny J. LeBlanc

发明人： Timothy M. Skergan ,  Johnny J. LeBlanc

IPC分类号： G06F104

CPC分类号： G01R31/318552

摘要： A method and apparatus for pipelining clock control signals across a chip. The present invention avoids the need for multiple clock distribution systems by allowing clock controls for clock stopping, scanning, and debugging to be distributed to all local clock buffers through pipelined non-scan latches. The test control pipeline latches may be routed along with the clock through the clock receiver, the central clock buffer, and the sector buffer areas of the chip. A relatively low speed testing mechanism may be used to drive the testing of the chip externally. The test clock is synchronized with a free-running clock on the chip to allow the circuit to be operated at speed during the testing of the chip. During boundary scan, the pipelined controls are forced to static levels which are active levels for scanning. Non-pipelined signals control the boundary scan operation based directly on the TCK clock defined in the IEEE 1149.1 boundary scan standard.

摘要翻译： 一种用于在芯片上流水线时钟控制信号的方法和装置。 本发明通过允许通过流水线非扫描锁存器将时钟停止，扫描和调试的时钟控制分配到所有本地时钟缓冲器来避免对多个时钟分配系统的需要。 测试控制流水线锁存器可以通过时钟接收器，中央时钟缓冲器和芯片的扇区缓冲器区域与时钟一起布线。 可以使用相对低速的测试机构来驱动芯片的外部测试。 测试时钟与芯片上的自由运行时钟同步，以允许电路在芯片测试期间以速度运行。 在边界扫描期间，流水线控件被强制为静态级别，这些级别是扫描的有效级别。 非流水线信号基于IEEE 1149.1边界扫描标准中定义的TCK时钟控制边界扫描操作。

公开(公告)号：US5568380A

公开(公告)日：1996-10-22

申请号：US114267

申请日：1993-08-30

申请人： Timothy B. Brodnax ,  John S. Bialas, Jr. ,  Steven A. King ,  Johnny J. LeBlanc ,  Dale A. Rickard ,  Clark J. Spencer ,  Daniel L. Stanley

发明人： Timothy B. Brodnax ,  John S. Bialas, Jr. ,  Steven A. King ,  Johnny J. LeBlanc ,  Dale A. Rickard ,  Clark J. Spencer ,  Daniel L. Stanley

IPC分类号： G01R31/3185 ,  G06F11/14 ,  G05B9/02

CPC分类号： G01R31/318533 ,  G06F11/1407

摘要： A fault-tolerant computer system having shadow registers for storing the contents of a primary array into a shadow array at the completion of a stored instruction execution. This is accomplished in one clock cycle with all registers being shadowed simultaneously. During rollback of execution steps for a checkpoint retry, the shadow register files provide a signal cycle unload of the shadow array into the primary array. LSSD latches are used in the shadow register file.

摘要翻译： 具有影子寄存器的容错计算机系统，用于在存储的指令执行完成时将主阵列的内容存储到阴影阵列中。 这是在一个时钟周期内实现的，所有寄存器同时被遮蔽。 在回滚检查点重试的执行步骤期间，影子寄存器文件将阴影阵列的信号循环卸载到主阵列中。 影子寄存器文件中使用LSSD锁存器。

公开(公告)号：US08214170B2

公开(公告)日：2012-07-03

申请号：US12354063

申请日：2009-01-15

申请人： Patrick R. Crosby ,  Daniel W. Cervantes ,  Johnny J. LeBlanc ,  Samuel I. Ward

发明人： Patrick R. Crosby ,  Daniel W. Cervantes ,  Johnny J. LeBlanc ,  Samuel I. Ward

IPC分类号： G01R31/14

CPC分类号： G01R31/318547

摘要： A method for test pattern compression generates a first test pattern comprising a plurality of bits. The method identifies bits comprising a don't-care bit value in the first test pattern and replaces the identified bit values with random bit values, to generate a second test pattern. The method determines a fault coverage level of the second test pattern. In the event the determined fault coverage level of the second test pattern exceeds a predetermined individual test pattern fault coverage level, for at least one bit position in the second test pattern corresponding to a replaced identified bit value and detecting at least one fault, the method exchanges the don't care value in the bit position in the first test pattern with the bit value in the corresponding bit position in the second test pattern. The method merges subsequent test patterns that increase fault coverage with the second test pattern.

摘要翻译： 测试图案压缩的方法产生包括多个位的第一测试图案。 该方法识别在第一测试模式中包含不关心位值的位，并且用随机位值替换所识别的位值，以产生第二测试模式。 该方法确定第二测试模式的故障覆盖水平。 在第二测试模式的所确定的故障覆盖水平超过预定的单独测试模式故障覆盖水平的情况下，对于与替换的所识别的位值相对应的第二测试模式中的至少一个位位置并检测至少一个故障，该方法 在第一测试模式中的位位置交换不关心值的第二测试模式中相应位位置的位值。 该方法将随后的测试模式合并，以增加第二个测试模式的故障覆盖。

公开(公告)号：US06452435B1

公开(公告)日：2002-09-17

申请号：US09436112

申请日：1999-11-08

申请人： Timothy M. Skergan ,  Johnny J. LeBlanc

发明人： Timothy M. Skergan ,  Johnny J. LeBlanc

IPC分类号： G06F104

CPC分类号： G06F1/10

摘要： A method and apparatus for pipelining clock control signals across a chip. The present invention avoids the need for multiple clock distribution systems by allowing clock controls for clock stopping, scanning, and debugging to be distributed to all local clock buffers through pipelined non-scan latches. The test control pipeline latches may be routed along with the clock through the clock receiver, the central clock buffer, and the sector buffer areas of the chip. A relatively low speed testing mechanism may be used to drive the testing of the chip externally. The test clock control signals are synchronized with a free-running clock on the chip to allow the circuit to be operated at speed during the testing of the chip.

摘要翻译： 一种用于在芯片上流水线时钟控制信号的方法和装置。 本发明通过允许通过流水线非扫描锁存器将时钟停止，扫描和调试的时钟控制分配到所有本地时钟缓冲器来避免对多个时钟分配系统的需要。 测试控制流水线锁存器可以通过时钟接收器，中央时钟缓冲器和芯片的扇区缓冲器区域与时钟一起布线。 可以使用相对低速的测试机构来驱动芯片的外部测试。 测试时钟控制信号与芯片上的自由运行时钟同步，以允许电路在芯片测试期间以速度运行。