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    Methods of making lateral junction field effect transistors using selective epitaxial growth
    3.
    发明授权
    Methods of making lateral junction field effect transistors using selective epitaxial growth 有权
    使用选择性外延生长制造横向结型场效应晶体管的方法

    公开(公告)号：US07560325B1

    公开(公告)日：2009-07-14

    申请号：US12102382

    申请日：2008-04-14

    申请人： Joseph Neil Merrett ,  Igor Sankin

    发明人： Joseph Neil Merrett ,  Igor Sankin

    IPC分类号： H01L21/337 ,  H01L29/80

    CPC分类号： H01L29/808 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66901

    摘要： Methods of making a semiconductor device such as a lateral junction field effect transistor (JFET) are described. The methods are self-aligned and involve selective epitaxial growth using a regrowth mask material to form the gate or the source/drain regions of the device. The methods can eliminate the need for ion implantation. The device can be made from a wide band-gap semiconductor material such as SiC. The regrowth mask material can be TaC. The devices can be used in harsh environments including applications involving exposure to radiation and/or high temperatures.

    摘要翻译： 描述制造诸如横向结型场效应晶体管（JFET）的半导体器件的方法。 这些方法是自对准的，并且涉及使用再生长掩模材料选择性地外延生长以形成器件的栅极或源极/漏极区域。 该方法可以消除离子注入的需要。 该器件可以由诸如SiC的宽带隙半导体材料制成。 再生面膜材料可以是TaC。 该设备可用于恶劣环境，包括涉及辐射和/或高温的应用。

    Semiconductor device with surge current protection and method of making the same
    4.
    发明申请
    Semiconductor device with surge current protection and method of making the same 有权
    具有浪涌电流保护的半导体器件及其制造方法

    公开(公告)号：US20080160685A1

    公开(公告)日：2008-07-03

    申请号：US11819646

    申请日：2007-06-28

    申请人： Igor Sankin ,  Joseph Neil Merrett

    发明人： Igor Sankin ,  Joseph Neil Merrett

    IPC分类号： H01L21/338

    CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/868

    摘要： A wide bandgap semiconductor device with surge current protection and a method of making the device are described. The device comprises a low doped n-type region formed by plasma etching through the first epitaxial layer grown on a heavily doped n-type substrate and a plurality of heavily doped p-type regions formed by plasma etching through the second epitaxial layer grown on the first epitaxial layer. Ohmic contacts are formed on p-type regions and on the backside of the n-type substrate. Schottky contacts are formed on the top surface of the n-type region. At normal operating conditions, the current in the device flows through the Schottky contacts. The device, however, is capable of withstanding extremely high current densities due to conductivity modulation caused by minority carrier injection from p-type regions.

    摘要翻译： 描述了具有浪涌电流保护的宽带隙半导体器件和制造该器件的方法。 该器件包括通过等离子体蚀刻形成的低掺杂n型区域，其通过在重掺杂n型衬底上生长的第一外延层和通过等离子体蚀刻形成的多个重掺杂p型区域形成，该区域通过在 第一外延层。 欧姆接触形成在p型区域和n型衬底的背面上。 在n型区域的顶表面上形成肖特基接触。 在正常工作条件下，器件中的电流流过肖特基触点。 然而，由于由p型区域的少数载流子注入引起的导电性调制，该器件能够承受极高的电流密度。

    Self-aligned trench field effect transistors with regrown gates and bipolar junction transistors with regrown base contact regions and methods of making
    5.
    发明授权
    Self-aligned trench field effect transistors with regrown gates and bipolar junction transistors with regrown base contact regions and methods of making 有权
    具有再生栅的自对准沟槽场效应晶体管和具有重新生长的基极接触区域的双极结型晶体管和制造方法

    公开(公告)号：US07314799B2

    公开(公告)日：2008-01-01

    申请号：US11293261

    申请日：2005-12-05

    申请人： Joseph Neil Merrett ,  Igor Sankin

    发明人： Joseph Neil Merrett ,  Igor Sankin

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66068 ,  H01L29/732 ,  H01L29/808

    摘要： Junction field-effect transistors with vertical channels and self-aligned regrown gates and methods of making these devices are described. The methods use techniques to selectively grow and/or selectively remove semiconductor material to form a p-n junction gate along the sides of the channel and on the bottom of trenches separating source fingers. Methods of making bipolar junction transistors with self-aligned regrown base contact regions and methods of making these devices are also described. The semiconductor devices can be made in silicon carbide.

    摘要翻译： 描述了具有垂直沟道和自对准再生栅的结型场效应晶体管和制造这些器件的方法。 所述方法使用技术来选择性地生长和/或选择性地去除半导体材料，以沿着沟道的侧面和分离源极指的沟槽的底部形成p-n结栅极。 还描述了制造具有自对准重新生长的基极接触区域的双极结型晶体管的方法以及制造这些器件的方法。 半导体器件可以制成碳化硅。

    Self-aligned trench field effect transistors with regrown gates and bipolar junction transistors with regrown base contact regions and methods of making
    6.
    发明授权
    Self-aligned trench field effect transistors with regrown gates and bipolar junction transistors with regrown base contact regions and methods of making 有权
    具有再生栅的自对准沟槽场效应晶体管和具有重新生长的基极接触区域的双极结型晶体管和制造方法

    公开(公告)号：US08729628B2

    公开(公告)日：2014-05-20

    申请号：US13585183

    申请日：2012-08-14

    申请人： Joseph Neil Merrett ,  Igor Sankin

    发明人： Joseph Neil Merrett ,  Igor Sankin

    IPC分类号： H01L29/78

    CPC分类号： H01L29/66068 ,  H01L29/732 ,  H01L29/808

    摘要： Junction field-effect transistors with vertical channels and self-aligned regrown gates and methods of making these devices are described. The methods use techniques to selectively grow and/or selectively remove semiconductor material to form a p-n junction gate along the sides of the channel and on the bottom of trenches separating source fingers. Methods of making bipolar junction transistors with self-aligned regrown base contact regions and methods of making these devices are also described. The semiconductor devices can be made in silicon carbide.

    摘要翻译： 描述了具有垂直沟道和自对准再生栅的结型场效应晶体管和制造这些器件的方法。 所述方法使用技术来选择性地生长和/或选择性地去除半导体材料，以沿着沟道的侧面和分离源极指的沟槽的底部形成p-n结栅极。 还描述了制造具有自对准重新生长的基极接触区域的双极结型晶体管的方法以及制造这些器件的方法。 半导体器件可以制成碳化硅。

    Semiconductor devices with non-punch-through semiconductor channels having enhanced conduction and methods of making
    7.
    发明授权
    Semiconductor devices with non-punch-through semiconductor channels having enhanced conduction and methods of making 有权
    具有非穿通半导体通道的半导体器件具有增强的传导和制造方法

    公开(公告)号：US08507335B2

    公开(公告)日：2013-08-13

    申请号：US13108505

    申请日：2011-05-16

    申请人： Igor Sankin ,  David C. Sheridan ,  Joseph Neil Merrett

    发明人： Igor Sankin ,  David C. Sheridan ,  Joseph Neil Merrett

    IPC分类号： H01L21/205

    CPC分类号： H01L29/8083 ,  H01L29/1058 ,  H01L29/1608 ,  H01L29/7392 ,  H01L29/7722

    摘要： Semiconductor devices are described wherein current flow in the device is confined between the rectifying junctions (e.g., p-n junctions or metal-semiconductor junctions). The device provides non-punch-through behavior and enhanced current conduction capability. The devices can be power semiconductor devices as such as Junction Field-Effect Transistors (VJFETs), Static Induction Transistors (SITs), Junction Field Effect Thyristors, or JFET current limiters. The devices can be made in wide bandgap semiconductors such as silicon carbide (SiC). According to some embodiments, the device can be a normally-off SiC vertical junction field effect transistor. Methods of making the devices and circuits comprising the devices are also described.

    摘要翻译： 描述了半导体器件，其中器件中的电流限制在整流结（例如，p-n结或金属 - 半导体结）之间。 该器件提供非穿通性能和增强的电流传导能力。 这些器件可以是功率半导体器件，例如接地场效应晶体管（VJFET），静态感应晶体管（SIT），结场效应晶闸管或JFET限流器。 这些器件可以制成宽带隙半导体，如碳化硅（SiC）。 根据一些实施例，器件可以是常关的SiC垂直结场效应晶体管。 还描述了制造包括装置的装置和电路的方法。

    SEMICONDUCTOR DEVICES WITH NON-PUNCH-THROUGH SEMICONDUCTOR CHANNELS HAVING ENHANCED CONDUCTION AND METHODS OF MAKING
    8.
    发明申请
    SEMICONDUCTOR DEVICES WITH NON-PUNCH-THROUGH SEMICONDUCTOR CHANNELS HAVING ENHANCED CONDUCTION AND METHODS OF MAKING 有权
    具有非穿孔半导体通道的半导体器件具有增强导电性和制造方法

    公开(公告)号：US20110217829A1

    公开(公告)日：2011-09-08

    申请号：US13108505

    申请日：2011-05-16

    申请人： Igor SANKIN ,  David C. SHERIDAN ,  Joseph Neil MERRETT

    发明人： Igor SANKIN ,  David C. SHERIDAN ,  Joseph Neil MERRETT

    IPC分类号： H01L21/205

    CPC分类号： H01L29/8083 ,  H01L29/1058 ,  H01L29/1608 ,  H01L29/7392 ,  H01L29/7722

    摘要： Semiconductor devices are described wherein current flow in the device is confined between the rectifying junctions (e.g., p-n junctions or metal-semiconductor junctions). The device provides non-punch-through behavior and enhanced current conduction capability. The devices can be power semiconductor devices as such as Junction Field-Effect Transistors (VJFETs), Static Induction Transistors (SITs), Junction Field Effect Thyristors, or JFET current limiters. The devices can be made in wide bandgap semiconductors such as silicon carbide (SiC). According to some embodiments, the device can be a normally-off SiC vertical junction field effect transistor. Methods of making the devices and circuits comprising the devices are also described.

    摘要翻译： 描述了半导体器件，其中器件中的电流限制在整流结（例如，p-n结或金属 - 半导体结）之间。 该器件提供非穿通性能和增强的电流传导能力。 这些器件可以是功率半导体器件，例如接地场效应晶体管（VJFET），静态感应晶体管（SIT），结场效应晶闸管或JFET限流器。 这些器件可以制成宽带隙半导体，如碳化硅（SiC）。 根据一些实施例，器件可以是常关的SiC垂直结场效应晶体管。 还描述了制造包括装置的装置和电路的方法。

    Method of making a semiconductor device with surge current protection
    9.
    发明授权
    Method of making a semiconductor device with surge current protection 有权
    制造具有浪涌电流保护的半导体器件的方法

    公开(公告)号：US07960198B2

    公开(公告)日：2011-06-14

    申请号：US11819646

    申请日：2007-06-28

    申请人： Igor Sankin ,  Joseph Neil Merrett

    发明人： Igor Sankin ,  Joseph Neil Merrett

    IPC分类号： H01L31/075 ,  H01L33/00

    CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/868

    摘要： A wide bandgap semiconductor device with surge current protection and a method of making the device are described. The device comprises a low doped n-type region formed by plasma etching through the first epitaxial layer grown on a heavily doped n-type substrate and a plurality of heavily doped p-type regions formed by plasma etching through the second epitaxial layer grown on the first epitaxial layer. Ohmic contacts are formed on p-type regions and on the backside of the n-type substrate. Schottky contacts are formed on the top surface of the n-type region. At normal operating conditions, the current in the device flows through the Schottky contacts. The device, however, is capable of withstanding extremely high current densities due to conductivity modulation caused by minority carrier injection from p-type regions.

    摘要翻译： 描述了具有浪涌电流保护的宽带隙半导体器件和制造该器件的方法。 该器件包括通过等离子体蚀刻形成的低掺杂n型区域，其通过在重掺杂n型衬底上生长的第一外延层和通过等离子体蚀刻形成的多个重掺杂p型区域形成，该区域通过在 第一外延层。 欧姆接触形成在p型区域和n型衬底的背面上。 在n型区域的顶表面上形成肖特基接触。 在正常工作条件下，器件中的电流流过肖特基触点。 然而，由于由p型区域的少数载流子注入引起的导电性调制，该器件能够承受极高的电流密度。