公开(公告)号：US11908686B2

公开(公告)日：2024-02-20

申请号：US17599668

申请日：2019-09-12

申请人： Enkris Semiconductor, Inc.

发明人： Kai Cheng

IPC分类号： H01L21/321 ,  H01L21/02 ,  H01L29/812

CPC分类号： H01L21/02389 ,  H01L21/0254 ,  H01L21/02458 ,  H01L21/3212 ,  H01L29/8122

摘要： The present application provides methods for manufacturing a vertical device. To begin with, a GaN-based semiconductor substrate is etched from a front surface to form a trench. Then, a P-type semiconductor layer and an N-type semiconductor layer are sequentially formed on a bottom wall and side walls of the trench and the front surface of the semiconductor substrate. The trench is partially filled with the P-type semiconductor layer. Thereafter, the N-type semiconductor layer and the P-type semiconductor layer are planarized, and the P-type semiconductor layer and the N-type semiconductor layer in the trench are retained. Next, a gate structure is formed at a gate area of the front surface of the semiconductor substrate, a source electrode is formed on two sides of the gate structure, and a drain electrode is formed on a rear surface of the semiconductor substrate respectively.

公开(公告)号：US20180342626A1

公开(公告)日：2018-11-29

申请号：US16036305

申请日：2018-07-16

申请人： United Silicon Carbide, Inc.

发明人： Zhongda Li ,  Anup Bhalla

IPC分类号： H01L29/812 ,  H01L21/04 ,  H01L29/808 ,  H01L29/66 ,  H01L29/47 ,  H01L29/45 ,  H01L29/16 ,  H01L29/10 ,  H01L29/06 ,  H01L21/768

CPC分类号： H01L29/8122 ,  H01L21/045 ,  H01L21/046 ,  H01L21/0465 ,  H01L21/047 ,  H01L21/0475 ,  H01L21/0485 ,  H01L21/76897 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/47 ,  H01L29/66007 ,  H01L29/66045 ,  H01L29/66068 ,  H01L29/665 ,  H01L29/66848 ,  H01L29/66856 ,  H01L29/66909 ,  H01L29/66969 ,  H01L29/8083 ,  H01L29/8128

摘要： A vertical JFET with a ladder termination may be made by a method using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A mask-less self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.

公开(公告)号：US20180204925A1

公开(公告)日：2018-07-19

申请号：US15920250

申请日：2018-03-13

申请人： Alfred I. Grayzel

发明人： Alfred I. Grayzel

IPC分类号： H01L29/423 ,  H01L29/40 ,  H01L29/10

CPC分类号： H01L29/7831 ,  H01L27/0629 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/1058 ,  H01L29/405 ,  H01L29/42376 ,  H01L29/7827 ,  H01L29/8083 ,  H01L29/8122 ,  H01L29/8124

摘要： A Field Effect Transistor includes a channel with one end designated the source and the other end designated the drain. The Field Effect Transistor also includes a means for connecting to said source end of said channel and a means for connecting to said drain end of said channel. A gate is divided into a plurality of segments each insulated from one another. A means for adjusting the bias of each of said segments independently of one another is configured whereby the depletion region in said channel can be adjusted to avoid pinch-off and to maximize the efficiency of said Field Effect Transistor.

公开(公告)号：US09966447B2

公开(公告)日：2018-05-08

申请号：US15456328

申请日：2017-03-10

申请人： Toyoda Gosei Co., Ltd.

发明人： Junya Nishii

IPC分类号： H01L29/423 ,  H01L29/78 ,  H01L29/51 ,  H01L21/28 ,  H01L21/02 ,  H01L29/66 ,  H01L29/812

CPC分类号： H01L29/4236 ,  H01L21/0228 ,  H01L21/0234 ,  H01L21/28185 ,  H01L21/28211 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/8122

摘要： A technique of manufacturing a semiconductor device of stable operation is provided. There is provided a method of manufacturing a semiconductor device comprising a first process of forming an insulating film from a nitrogen-containing organic metal used as raw material, on a semiconductor layer by atomic layer deposition; a second process of processing the insulating film by oxygen plasma treatment in an atmosphere including at least one of oxygen and ozone; and a third process of processing the insulating film by heat treatment in a nitrogen-containing atmosphere, after the second process.

公开(公告)号：US09685327B2

公开(公告)日：2017-06-20

申请号：US14460065

申请日：2014-08-14

申请人： SIXPOINT MATERIALS, INC. ,  Seoul Semiconductor Co., Ltd.

发明人： Tadao Hashimoto

IPC分类号： H01L21/02 ,  H01L29/20 ,  H01L29/207 ,  H01L29/78 ,  H01L29/812 ,  C23C16/30 ,  H01L29/861 ,  H01L29/872 ,  H01L29/205 ,  H01L29/32 ,  H01L29/66 ,  H01L29/778 ,  H01L29/201 ,  H01L29/417 ,  H01L29/06

CPC分类号： H01L21/0254 ,  C23C16/303 ,  H01L21/02389 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/02584 ,  H01L21/0262 ,  H01L21/02623 ,  H01L21/02694 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/207 ,  H01L29/32 ,  H01L29/41766 ,  H01L29/66462 ,  H01L29/7784 ,  H01L29/7828 ,  H01L29/8122 ,  H01L29/8611 ,  H01L29/872

摘要： The present invention discloses an electronic device using a group III nitride substrate fabricated via the ammonothermal method. By utilizing the high-electron concentration of ammonothermally grown substrates having the dislocation density less than 105 cm−2, combined with a high-purity active layer of Ga1-x-yAlxInyN (0≦x≦1, 0≦y≦1) grown by a vapor phase method, the device can attain high level of breakdown voltage as well as low on-resistance. To realize a good matching between the ammonothermally grown substrate and the high-purity active layer, a transition layer is optionally introduced. The active layer is thicker than a depletion region created by a device structure in the active layer.

公开(公告)号：US20150171078A1

公开(公告)日：2015-06-18

申请号：US14628721

申请日：2015-02-23

申请人： Infineon Technologies Austria AG

发明人： Daniel Kueck ,  Rudolf Elpelt

IPC分类号： H01L27/06 ,  H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/808 ,  H01L29/861

CPC分类号： H01L27/0629 ,  H01L29/0615 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/1608 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/42316 ,  H01L29/8083 ,  H01L29/8122 ,  H01L29/8613

摘要： A semiconductor device incudes a cell region and a contact region, the cell region including a functional unit including a gate electrode, a source and a drain electrode, and the contact region including a gate pad. The gate electrode, the gate pad and the source electrode are disposed on a first main surface of a semiconductor substrate, and the drain electrode is disposed on a second main surface of the semiconductor substrate, the second main surface being opposite to the first main surface. A shielding member is disposed between the gate pad and the drain electrode, the shielding member being electrically connected to the source electrode.

摘要翻译： 半导体器件包括单元区域和接触区域，单元区域包括包括栅电极，源极和漏极的功能单元，以及包括栅极焊盘的接触区域。 栅电极，栅极焊盘和源电极设置在半导体衬底的第一主表面上，漏电极设置在半导体衬底的第二主表面上，第二主表面与第一主表面相对 。 屏蔽部件设置在栅焊盘和漏电极之间，屏蔽部件与源电极电连接。

公开(公告)号：US08994078B2

公开(公告)日：2015-03-31

申请号：US13537180

申请日：2012-06-29

申请人： Daniel Kueck ,  Rudolf Elpelt

发明人： Daniel Kueck ,  Rudolf Elpelt

IPC分类号： H01L29/10 ,  H01L29/40 ,  H01L29/808 ,  H01L29/812 ,  H01L29/06 ,  H01L29/16

CPC分类号： H01L27/0629 ,  H01L29/0615 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/1608 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/42316 ,  H01L29/8083 ,  H01L29/8122 ,  H01L29/8613

摘要： A semiconductor device includes a cell region and a contact region, the cell region including a functional unit including a gate electrode, a source and a drain electrode, and the contact region including a gate pad. The gate electrode, the gate pad and the source electrode are disposed on a first main surface of a semiconductor substrate, and the drain electrode is disposed on a second main surface of the semiconductor substrate, the second main surface being opposite to the first main surface. A shielding member is disposed between the gate pad and the drain electrode, the shielding member being electrically connected to the source electrode.

摘要翻译： 半导体器件包括单元区域和接触区域，单元区域包括包括栅电极，源极和漏极的功能单元，以及包括栅极焊盘的接触区域。 栅电极，栅极焊盘和源电极设置在半导体衬底的第一主表面上，漏电极设置在半导体衬底的第二主表面上，第二主表面与第一主表面相对 。 屏蔽部件设置在栅焊盘和漏电极之间，屏蔽部件与源电极电连接。

公开(公告)号：US20140353667A1

公开(公告)日：2014-12-04

申请号：US13906738

申请日：2013-05-31

申请人： Infineon Technologies AG

发明人： Jens Konrath ,  Hans-Joachim Schulze ,  Roland Rupp ,  Wolfgang Werner ,  Frank Pfirsch

IPC分类号： H01L29/812 ,  H01L29/04 ,  H01L29/66 ,  H01L29/16

CPC分类号： H01L29/66909 ,  H01L29/04 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/47 ,  H01L29/66068 ,  H01L29/66431 ,  H01L29/66734 ,  H01L29/66787 ,  H01L29/66848 ,  H01L29/7827 ,  H01L29/8122 ,  H01L29/872

摘要： A field-effect semiconductor device having a semiconductor body with a main surface is provided. The semiconductor body includes, in a vertical cross-section substantially orthogonal to the main surface, a drift layer of a first conductivity type, a semiconductor mesa of the first conductivity type adjoining the drift layer, substantially extending to the main surface and having two side walls, and two second semiconductor regions of a second conductivity type arranged next to the semiconductor mesa. Each of the two second semiconductor regions forms a pn-junction at least with the drift layer. A rectifying junction is formed at least at one of the two side walls of the mesa. Further, a method for producing a heterojunction semiconductor device is provided.

摘要翻译： 提供了具有主表面的半导体本体的场效应半导体器件。 半导体本体在基本上垂直于主表面的垂直横截面中包括第一导电类型的漂移层，邻接漂移层的第一导电类型的半导体台面，基本上延伸到主表面并具有两个侧面 壁，以及布置在半导体台面旁边的第二导电类型的两个第二半导体区域。 两个第二半导体区域中的每一个至少与漂移层形成pn结。 在台面的两个侧壁中的至少一个侧面上形成整流结。 此外，提供了一种异质结半导体器件的制造方法。

公开(公告)号：US20130113028A2

公开(公告)日：2013-05-09

申请号：US13393002

申请日：2010-06-23

申请人： Hironobu MIYAMOTO ,  Yasuhiro OKAMOTO ,  Yuji ANDO ,  Tatsuo NAKAYAMA ,  Takashi INOUE ,  Kazuki OTA ,  Kazuomi ENDO

发明人： Hironobu MIYAMOTO ,  Yasuhiro OKAMOTO ,  Yuji ANDO ,  Tatsuo NAKAYAMA ,  Takashi INOUE ,  Kazuki OTA ,  Kazuomi ENDO

IPC分类号： H01L29/78

CPC分类号： H01L29/8122 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/7809 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/8128

摘要： A semiconductor device comprises a substrate 1, a first n-type semiconductor layer 21′, a second n-type semiconductor layer 23, a p-type semiconductor layer 24, and a third n-type semiconductor layer 25′, wherein the first n-type semiconductor layer 21′, the second n-type semiconductor layer 23, the p-type semiconductor layer 24, and the third n-type semiconductor layer 25′ are laminated at the upper side of the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 21′ and the source electrode 12 is in ohmic-contact with the third n-type semiconductor layer 25′. A gate electrode 14 is arranged so as to fill an opening portion to be filled that extends from the third n-type semiconductor layer 25′ to the second n-type semiconductor layer 23, and the gate electrode 14 is in contact with the upper surface of the second n-type semiconductor layer 23, the side surfaces of the p-type semiconductor layer 24, and the side surfaces of the third n-type semiconductor layer 25′. The second n-type semiconductor layer 23 has composition that changes from the drain electrode 13 side toward the source electrode 12 side in the direction perpendicular to the plane of the substrate 1 and contains donor impurity.

摘要翻译： 半导体器件包括衬底1，第一n型半导体层21'，第二n型半导体层23，p型半导体层24和第三n型半导体层25'，其中第一n型半导体层 型半导体层21'，第二n型半导体层23，p型半导体层24和第三n型半导体层25'依次层叠在基板1的上侧。 漏电极13与第一n型半导体层21'欧姆接触，源电极12与第三n型半导体层25'欧姆接触。 栅电极14被布置成填充从第三n型半导体层25'延伸到第二n型半导体层23的待填充的开口部分，并且栅电极14与上表面 第二n型半导体层23，p型半导体层24的侧表面和第三n型半导体层25'的侧表面。 第二n型半导体层23具有从垂直于基板1的平面的方向从漏电极13侧向源电极12侧变化的成分，并且含有施主杂质。

公开(公告)号：US20080128862A1

公开(公告)日：2008-06-05

申请号：US11667735

申请日：2005-11-14

申请人： Masahiro Sugimoto ,  Tsutomu Uesugi ,  Hiroyuki Ueda ,  Narumasa Soejima ,  Tetsu Kachi

发明人： Masahiro Sugimoto ,  Tsutomu Uesugi ,  Hiroyuki Ueda ,  Narumasa Soejima ,  Tetsu Kachi

IPC分类号： H01L21/20 ,  H01L29/20

CPC分类号： H01L29/7802 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/0891 ,  H01L29/2003 ,  H01L29/41 ,  H01L29/778 ,  H01L29/7788 ,  H01L29/8122

摘要： A semiconductor device is provided with a drain electrode 22, a semiconductor base plate 32, an electric current regulation layer 42 covering a part of a surface of the semiconductor base plate 32 and leaving a non-covered surface 55 at the surface of the semiconductor base plate 32, a semiconductor layer 50 covering a surface of the electric current regulation layer 42, and a source electrode 62 formed at a surface of the semiconductor layer 50. A drift region 56, a channel forming region 54, and a source region 52 are formed within the semiconductor layer 50. The drain electrode 22 is connected to a first terminal of a power source, and the source electrode 62 is connected to a second terminal of the power source. With this semiconductor layer 50, it is possible to increase withstand voltage or reduce the occurrence of current leakage.

摘要翻译： 半导体器件设置有漏电极22，半导体基板32，覆盖半导体基板32的一部分表面的电流调节层42，并在半导体基板的表面留下未被覆盖的表面55 板32，覆盖电流调节层42的表面的半导体层50和形成在半导体层50的表面的源电极62。 在半导体层50内形成有漂移区56，沟道形成区54和源极区52。 漏电极22连接到电源的第一端子，源电极62连接到电源的第二端子。 利用该半导体层50，可以提高耐压或减少电流泄漏的发生。