公开(公告)号：US07259463B2

公开(公告)日：2007-08-21

申请号：US11004767

申请日：2004-12-03

Applicant: Jui Jen Huang ,  Minghsing Tsai ,  Shau-Lin Shue ,  Hung-Wen Su ,  Ting-Chu Ko

Inventor： Jui Jen Huang ,  Minghsing Tsai ,  Shau-Lin Shue ,  Hung-Wen Su ,  Ting-Chu Ko

IPC: H01L23/48

CPC classification number: H01L21/76838 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming an integrated circuit interconnect structure is presented. A first conductive line is formed over a semiconductor substrate. A conductive cap layer is formed on the first conductive line to improve device reliability. An etch stop layer (ESL) is formed on the conductive cap layer. An inter-level dielectric (IMD) is formed on the ESL. A via opening and a trench are formed in the ESL, IMD, and conductive cap layer. A recess is formed in the first conductive line. The recess can be formed by over etching when the first dielectric is etched, or by a separate process such as argon sputtering. A second conductive line is formed filling the trench, opening and recess.

Abstract translation: 提出了一种形成集成电路互连结构的方法。 在半导体衬底上形成第一导电线。 导电盖层形成在第一导电线上以提高器件的可靠性。 在导电盖层上形成蚀刻停止层（ESL）。 在ESL上形成层间电介质（IMD）。 通孔和沟槽形成在ESL，IMD和导电盖层中。 在第一导线中形成凹部。 当蚀刻第一电介质时，或者通过诸如氩气溅射的分离工艺，可以通过过蚀刻形成凹部。 形成第二导电线，填充沟槽，开口和凹陷。