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1.发明申请MEMORY CONTROLLERS, MEMORY SYSTEMS, SOLID STATE DRIVES AND METHODS FOR PROCESSING A NUMBER OF COMMANDS 有权存储器控制器，存储器系统，固态驱动器和处理多个命令的方法公开(公告)号：US20120324180A1
公开(公告)日：2012-12-20
申请号：US13599594
申请日：2012-08-30
IPC分类号： G06F12/00
CPC分类号： G06F3/061 , G06F3/0659 , G06F3/067 , G06F3/0679 , G06F3/0688 , G06F13/161 , G06F13/28
摘要： The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.
摘要翻译： 本公开包括用于存储器控制器的方法和装置。 在一个或多个实施例中，存储器控制器包括多个后端通道，以及通信地耦合到多个后端通道的命令队列。 命令队列配置为保存从主机接收的主机命令。 电路被配置为至少响应于命令队列中的主机命令的数量生成多个后端命令，并且将后端命令的数量分配给多个后端信道的数量。
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公开(公告)号：US20120011335A1
公开(公告)日：2012-01-12
申请号：US13242535
申请日：2011-09-23
IPC分类号： G06F12/00
CPC分类号： G06F3/061 , G06F3/0659 , G06F3/067 , G06F3/0679 , G06F3/0688 , G06F13/161 , G06F13/28
摘要： The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.
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3.发明授权Memory controllers, memory systems, solid state drives and methods for processing a number of commands 有权存储器控制器，存储器系统，固态驱动器以及用于处理多个命令的方法公开(公告)号：US08055816B2
公开(公告)日：2011-11-08
申请号：US12421093
申请日：2009-04-09
CPC分类号： G06F3/061 , G06F3/0659 , G06F3/067 , G06F3/0679 , G06F3/0688 , G06F13/161 , G06F13/28
摘要： The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.
摘要翻译： 本公开包括用于存储器控制器的方法和装置。 在一个或多个实施例中，存储器控制器包括多个后端通道，以及通信地耦合到多个后端通道的命令队列。 命令队列配置为保存从主机接收的主机命令。 电路被配置为至少响应于命令队列中的主机命令的数量生成多个后端命令，并且将后端命令的数量分配给多个后端信道的数量。
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公开(公告)号：US20100211834A1
公开(公告)日：2010-08-19
申请号：US12388305
申请日：2009-02-18
CPC分类号： G06F11/1048 , G06F11/10 , G06F11/1004 , G06F13/28 , G06F21/64 , G11C2029/0411 , H03M13/09 , H03M13/13 , H03M13/29
摘要： The present disclosure includes methods, devices, and systems for data integrity in memory controllers. One memory controller embodiment includes a host interface and first error detection circuitry coupled to the host interface. The memory controller can include a memory interface and second error detection circuitry coupled to the memory interface. The first error detection circuitry can be configured to calculate error detection data for data received from the host interface and to check the integrity of data transmitted to the host interface. The second error detection circuitry can be configured to calculate error correction data for data and first error correction data transmitted to the memory interface and to check integrity of data and first error correction data received from the memory interface.
摘要翻译： 本公开包括用于存储器控制器中的数据完整性的方法，设备和系统。 一个存储器控制器实施例包括耦合到主机接口的主机接口和第一错误检测电路。 存储器控制器可以包括耦合到存储器接口的存储器接口和第二错误检测电路。 第一错误检测电路可以被配置为计算从主机接口接收的数据的错误检测数据，并且检查发送到主机接口的数据的完整性。 第二错误检测电路可以被配置为计算发送到存储器接口的数据和第一纠错数据的纠错数据，并且检查数据的完整性和从存储器接口接收到的第一纠错数据。
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公开(公告)号：US08468417B2
公开(公告)日：2013-06-18
申请号：US12388305
申请日：2009-02-18
IPC分类号： H03M13/00
CPC分类号： G06F11/1048 , G06F11/10 , G06F11/1004 , G06F13/28 , G06F21/64 , G11C2029/0411 , H03M13/09 , H03M13/13 , H03M13/29
摘要： The present disclosure includes methods, devices, and systems for data integrity in memory controllers. One memory controller embodiment includes a host interface and first error detection circuitry coupled to the host interface. The memory controller can include a memory interface and second error detection circuitry coupled to the memory interface. The first error detection circuitry can be configured to calculate error detection data for data received from the host interface and to check the integrity of data transmitted to the host interface. The second error detection circuitry can be configured to calculate error correction data for data and first error correction data transmitted to the memory interface and to check integrity of data and first error correction data received from the memory interface.
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6.发明申请MEMORY CONTROLLERS, MEMORY SYSTEMS, SOLID STATE DRIVES AND METHODS FOR PROCESSING A NUMBER OF COMMANDS 有权存储器控制器，存储器系统，固态驱动器和处理多个命令的方法公开(公告)号：US20100262721A1
公开(公告)日：2010-10-14
申请号：US12421093
申请日：2009-04-09
CPC分类号： G06F3/061 , G06F3/0659 , G06F3/067 , G06F3/0679 , G06F3/0688 , G06F13/161 , G06F13/28
摘要： The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.
摘要翻译： 本公开包括用于存储器控制器的方法和装置。 在一个或多个实施例中，存储器控制器包括多个后端通道，以及通信地耦合到多个后端通道的命令队列。 命令队列配置为保存从主机接收的主机命令。 电路被配置为至少响应于命令队列中的主机命令的数量生成多个后端命令，并且将后端命令的数量分配给多个后端信道的数量。
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