摘要:
An Access Point (“AP”) apparatus comprising one or more processors containing program code. The program code may be configured to: (i) cause the AP to broadcast a beacon containing a single SSID indentifying the AP; (ii) cause the AP to receive from the STA an query for network information for at least one network operator accessible through the AP; and (iii) cause the AP to send to the STA, for the at least one network operator, a network information description element, in response to the network information query. The AP providing the plural responses broadcasts only a single service set identification (“SSID”).
摘要:
In a multi-processor system with a high degree of inter processor communication, an operating system extension is described as a kernel function to poll a receive buffer. This is an opportunistic poll that continues to run in the user context after an application process has invoked the kernel with a blocking receive function. It is also running whenever no higher priority task is running. New data packets may be received for the present user application process while avoiding context switches, and for a different user process while avoiding interrupts. A hardware implemented delay timer and a buffer fill monitor generate interrupts when the system is not polling, thus guaranteeing a maximum latency and preventing buffer overflow, but these interrupts are largely avoided by polling when the system is handling a large amount of inter processor data traffic.
摘要:
A protocol suite for inter-process communication in multi-process and multi-computer environments is described which supports one or more loosely flow-controlled connections to be established over a tightly flow-controlled connection. The tightly flow-controlled connections between processes provide a reliable underlying network between the members of a multiprocessing environment over which multi-computer applications can then efficiently communicate by setting up loosely flow-controlled connections.
摘要:
A method is described for one-to-all route selection in Communications Networks with multiple QoS metrics. This method takes a first metric (say, delay) as a constraint and a second metric (say, cost) as an optimization target. A potential objective is to find a path between a source node and each node in a communications network such that the delay of the path does not exceed a path delay constraint and the cost of the path is minimized. The method selects a first path which is a shortest path from a source node to each node in terms of the first metric using Dijkstra's algorithm. A reachability graph is then constructed based on the first metric path constraint. Within the reachability graph, another path is found, which is a shortest path from a source node to each node in terms of the second metric, using Dijkstra's algorithm. Any path to a particular node selected within the reachability graph replaces the first path to said particular node. This method can guarantee to find a nearly optimal path with the given constraint satisfied as long as there exists such a path.
摘要:
A protocol element referred to as a secure handle is described which provides an efficient and reliable method for application-to-application signaling in multi-process and multi-computer environments. The secure handle includes an absolute memory reference which allows the kernel to more quickly and efficiently associate a network data packet with an application's communication context in the kernel.
摘要:
An embodiment of one of the inventions disclosed herein is a computer system that includes a plurality of interconnected computational hosts, each of which are connected to one of a plurality of buffers. Each of the buffers includes a plurality of buffer spaces. Each of the computational hosts may be configured such that each transfer of a data packet from one of the plurality of computational hosts acting as a source of the data packet to another one of the plurality of computational hosts acting as a destination of the data packet is controlled by an availability of buffer spaces in the buffer coupled to the destination computational host.
摘要:
A system and method allows a virtual server to be assigned to any of a plurality of physical computes hosts in a networked computing system. Each physical compute host includes a motherboard and a secure management controller that includes a secure memory vault for storing virtual server secure profile data and a BIOS switch for loading a BIOS memory with a BIOS image from the secure memory and controlling access to the BIOS memory by the motherboard. The virtual server secure profile data is transmitted to the secure memory under the exclusive control of a secure infrastructure layer including a common system controller a secure network that is distinct from the network over which the operating system and application stack is loaded.
摘要:
A high performance network adapter is provided for forwarding traffic and providing adaptation between packetized memory fragment based processor links of multiple CPUs and multiple switch planes of a packet switching network. Low latency for short and long packets is provided by innovative packet reassembly, overlapping transmission, and reverse order transmission in the upstream direction, and cut through operation in the downstream direction.
摘要:
An embodiment of one of the inventions disclosed herein is a computer system that includes a plurality of interconnected computational hosts, each of which are connected to one of a plurality of buffers. Each of the buffers includes a plurality of buffer spaces. Each of the computational hosts may be configured such that each transfer of a data packet from one of the plurality of computational hosts acting as a source of the data packet to another one of the plurality of computational hosts acting as a destination of the data packet is controlled by an availability of buffer spaces in the buffer coupled to the destination computational host.
摘要:
Embodiments of the present invention include enhanced functionalities and components within a Communication Endpoint Processor (CEP) that act as an interface between computational and communications domains. The embodiments disclosed herein deliver a complete memory mapped high performance interface that has the ability to support the simultaneous transmission of multiple frames of multiple sizes, and that has the ability to interrupt the transmission of lower priority frames in order to send higher priority frames.