公开(公告)号：US07516312B2

公开(公告)日：2009-04-07

申请号：US10817263

申请日：2004-04-02

申请人： Hong Wang ,  Ralph Kling ,  Edward T. Grochowski ,  Kalpana Ramakrishnan

发明人： Hong Wang ,  Ralph Kling ,  Edward T. Grochowski ,  Kalpana Ramakrishnan

IPC分类号： G06F15/00 ,  G06F9/00

CPC分类号： G06F9/3806 ,  G06F9/30054 ,  G06F9/3848

摘要： An instruction prefetch apparatus includes a branch target buffer (BTB), a presbyopic target buffer (PTB) and a prefetch stream buffer (PSB). The BTB includes records that map branch addresses to branch target addresses, and the PTB includes records that map branch target addresses to subsequent branch target addresses. When a branch instruction is encountered, the BTB can predict the dynamically adjacent subsequent block entry location as the branch target address in the record that also includes the branch instruction address. The PTB can predict multiple subsequent blocks by mapping the branch target address to subsequent dynamic blocks. The PSB holds instructions prefetched from subsequent blocks predicted by the PTB.

摘要翻译： 指令预取装置包括分支目标缓冲器（BTB），远视目标缓冲器（PTB）和预取流缓冲器（PSB）。 BTB包括将分支地址映射到分支目标地址的记录，PTB包括将分支目标地址映射到后续分支目标地址的记录。 当遇到分支指令时，BTB可以将动态相邻的后续块条目位置预测为记录中还包括分支指令地址的分支目标地址。 PTB可以通过将分支目标地址映射到后续动态块来预测多个后续块。 PSB保存由PTB预测的后续块预取的指令。

公开(公告)号：US06732260B1

公开(公告)日：2004-05-04

申请号：US09518939

申请日：2000-03-06

申请人： Hong Wang ,  Ralph Kling ,  Edward T. Grochowski ,  Kalpana Ramakrishnan

发明人： Hong Wang ,  Ralph Kling ,  Edward T. Grochowski ,  Kalpana Ramakrishnan

IPC分类号： G06F1500

CPC分类号： G06F9/3806 ,  G06F9/30054 ,  G06F9/3848

摘要： An instruction prefetch apparatus includes a branch target buffer (BTB), a presbyopic target buffer (PTB) and a prefetch stream buffer (PSB). The BTB includes records that map branch addresses to branch target addresses, and the PTB includes records that map branch target addresses to subsequent branch target addresses. When a branch instruction is encountered, the BTB can predict the dynamically adjacent subsequent block entry location as the branch target address in the record that also includes the branch instruction address. The PTB can predict multiple subsequent blocks by mapping the branch target address to subsequent dynamic blocks. The PSB holds instructions prefetched from subsequent blocks predicted by the PTB.

公开(公告)号：US6012134A

公开(公告)日：2000-01-04

申请号：US57968

申请日：1998-04-09

申请人： Rory McInerney ,  Eric Sindelar ,  Tse-Yu Yeh ,  Kalpana Ramakrishnan

发明人： Rory McInerney ,  Eric Sindelar ,  Tse-Yu Yeh ,  Kalpana Ramakrishnan

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F9/34

CPC分类号： G06F9/382 ,  G06F12/0862 ,  G06F9/3802 ,  G06F9/3808 ,  G06F9/3814 ,  G06F9/3844 ,  G06F2212/6022

摘要： A computer processor with a mechanism for improved prefetching of instrucns into a local cache includes an instruction pointer multiplexer that generates one of a plurality of instruction pointers in a first pipeline stage, which is used to produce a physical address from an ITLB lookup. A comparison is performed by compare logic between the physical address (and tags) of a set in the local cache and the set associated with the selected instruction pointer. A way multiplexer selects the proper way output from either the compare logic or an instruction streaming buffer that stores instructions returned from the first cache, but not yet written into the local cache. An instruction is bypassed to the way multiplexer from the instruction streaming buffer in response to an instruction streaming buffer hit and a miss signal by the compare logic.

摘要翻译： 具有用于将指令改进预取到本地高速缓存中的机制的计算机处理器包括指令指针多路复用器，其在第一流水线级中生成多个指令指针之一，其用于从ITLB查找产生物理地址。 通过本地缓存中的集合的物理地址（和标签）与与所选择的指令指针相关联的集合之间的比较逻辑执行比较。 方式多路复用器从存储从第一高速缓存返回但尚未写入本地高速缓存的指令的比较逻辑或指令流缓冲器中选择正确的方式输出。 响应于指令流缓冲器命中和比较逻辑的未命中信号，指令被旁路到来自指令流缓冲器的多路复用器的方式。