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    Placing partitioned circuit designs within iterative implementation flows
    1.
    发明授权
    Placing partitioned circuit designs within iterative implementation flows 有权
    将分隔电路设计放在迭代实现流程中

    公开(公告)号：US07590960B1

    公开(公告)日：2009-09-15

    申请号：US11787925

    申请日：2007-04-18

    申请人： Raymond Kong ,  Navaratnasothie Selvakkumaran ,  Kamal Chaudhary

    发明人： Raymond Kong ,  Navaratnasothie Selvakkumaran ,  Kamal Chaudhary

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054 ,  G06F17/5072

    摘要： A method of placing circuit elements of a partitioned circuit design on a target programmable logic device (PLD) can include mapping circuit elements of the circuit design to corresponding partitions of the circuit design, selecting a circuit element of the circuit design, and selecting a candidate location within a logic boundary on the target PLD. The method also can include validating the candidate location for the selected circuit element, at least in part, according to whether the selected circuit element belongs to a same partition of the circuit design as at least one other circuit element already placed within the logic boundary. The selected circuit element can be selectively placed at the candidate location according to the validation.

    摘要翻译： 将分割电路设计的电路元件放置在目标可编程逻辑器件（PLD）上的方法可以包括将电路设计的电路元件映射到电路设计的相应分区，选择电路设计的电路元件，以及选择候选 位于目标PLD的逻辑边界内。 该方法还可以包括至少部分地根据所选择的电路元件是否属于与已经放置在逻辑边界内的至少一个其它电路元件的电路设计的相同分区来验证所选择的电路元件的候选位置。 所选择的电路元件可以根据验证选择性地放置在候选位置。

    Latch based optimization during implementation of circuit designs for programmable logic devices
    3.
    发明授权
    Latch based optimization during implementation of circuit designs for programmable logic devices 有权
    实现可编程逻辑器件电路设计时的基于锁存器的优化

    公开(公告)号：US08146041B1

    公开(公告)日：2012-03-27

    申请号：US13180782

    申请日：2011-07-12

    申请人： Sankaranarayanan Srinivasan ,  Sridhar Krishnamurthy ,  Brian D. Philofsky ,  Kamal Chaudhary ,  Anirban Rahut

    发明人： Sankaranarayanan Srinivasan ,  Sridhar Krishnamurthy ,  Brian D. Philofsky ,  Kamal Chaudhary ,  Anirban Rahut

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F17/505

    摘要： A computer-implemented method of implementing a circuit design within a programmable logic device can include selecting at least one circuit element of the circuit design. The selected circuit element can be converted to a latch. A timing analysis can be performed upon the circuit design after conversion of the selected circuit element to a latch. A determination can be made by a computer as to whether the timing of the circuit design improves and the conversion of the selected circuit element to a latch can be accepted when the timing of the circuit design improves. The circuit design can be output.

    摘要翻译： 实现可编程逻辑器件内的电路设计的计算机实现的方法可以包括选择电路设计的至少一个电路元件。 所选择的电路元件可以被转换成锁存器。 在将所选择的电路元件转换为锁存器之后，可以在电路设计上执行时序分析。 当电路设计的时序改善时，计算机可以确定电路设计的时序是否改善，并且可以接受所选择的电路元件到锁存器的转换。 可以输出电路设计。

    Congestion estimation for programmable logic devices
    4.
    发明授权
    Congestion estimation for programmable logic devices 失效
    可编程逻辑器件的拥塞估计

    公开(公告)号：US07146590B1

    公开(公告)日：2006-12-05

    申请号：US10927734

    申请日：2004-08-27

    申请人： Kamal Chaudhary

    发明人： Kamal Chaudhary

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077

    摘要： A method of estimating congestion for a programmable logic device can include calculating a number of fan-in paths for each resource in the programmable logic device and calculating a number of fan-out paths for each resource in the programmable logic device. For each resource of the programmable logic device, a number of paths having different path characteristics can be determined and a probability can be assigned thereto. One or more measures of congestion can be computed according to the determining step.

    摘要翻译： 估计可编程逻辑器件的拥塞的方法可以包括为可编程逻辑器件中的每个资源计算多个扇入路径，并为可编程逻辑器件中的每个资源计算多个扇出路径。 对于可编程逻辑器件的每个资源，可以确定具有不同路径特性的多个路径，并且可以分配概率。 可以根据确定步骤计算拥塞的一个或多个措施。

    Method for analytical placement of cells using density surface representations
    5.
    发明授权
    Method for analytical placement of cells using density surface representations 有权
    使用密度表面表示法分析细胞的方法

    公开(公告)号：US06415425B1

    公开(公告)日：2002-07-02

    申请号：US09262727

    申请日：1999-03-04

    申请人： Kamal Chaudhary ,  Sudip K. Nag

    发明人： Kamal Chaudhary ,  Sudip K. Nag

    IPC分类号： G06F1750

    CPC分类号： G06F17/5072

    摘要： A method for analytical placement of cells using density surface representations. The placement of the cells is characterized as density surface fun which is two-dimensional and continuous. The cells are iteratively moved from areas having higher densities of placed cells to areas having lower densities of placed cells using the density surface function.

    摘要翻译： 使用密度表面表示法分析细胞的方法。 细胞的放置被表征为二维和连续的密度表面乐趣。 使用密度表面函数将细胞从具有较高密度的放置细胞的区域迭代地移动到具有较低密度的置换细胞的区域。

    Incremental placement during physical synthesis
    7.
    发明授权
    Incremental placement during physical synthesis 有权
    物理合成过程中的增量放置

    公开(公告)号：US07536661B1

    公开(公告)日：2009-05-19

    申请号：US11361370

    申请日：2006-02-24

    申请人： Amit Singh ,  Kamal Chaudhary

    发明人： Amit Singh ,  Kamal Chaudhary

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072

    摘要： A method of optimizing a portion of a circuit design for a target device can include identifying a critical region from a plurality of regions after an initial placement of the circuit design. The critical region can be defined, at least in part, by at least one input block and at least one output block. Blocks of the critical region can be relocated to different sites within the critical region. The method further can include evaluating the relocation of blocks of the critical region according to a cost function and continuing to relocate blocks and evaluate the relocation of blocks in the critical region until at least one exit criterion is met.

    摘要翻译： 优化目标设备的电路设计的一部分的方法可以包括在电路设计的初始放置之后从多个区域识别关键区域。 关键区域可以至少部分地由至少一个输入块和至少一个输出块来定义。 关键区域的块可以重新定位到关键区域内的不同位置。 该方法还可以包括根据成本函数评估关键区域的块的重新定位，并且继续重新定位块并评估临界区域中块的重定位，直到满足至少一个退出准则。

    Delay optimized mapping for programmable gate arrays with multiple sized lookup tables
    8.
    发明授权
    Delay optimized mapping for programmable gate arrays with multiple sized lookup tables 有权
    对具有多个大小的查找表的可编程门阵列进行延迟优化映射

    公开(公告)号：US06336208B1

    公开(公告)日：2002-01-01

    申请号：US09244662

    申请日：1999-02-04

    申请人： Sundararajarao Mohan ,  Kamal Chaudhary

    发明人： Sundararajarao Mohan ,  Kamal Chaudhary

    IPC分类号： G06F1750

    CPC分类号： G06F17/5054

    摘要： A process for mapping logic nodes to a plurality of sizes of lookup tables in a programmable gate array. A node and its predecessor nodes are selectively collapsed into a first single node as a function of delay factors associated with the plurality of sizes of lookup tables and a maximum of delay factors associated with the predecessor nodes. If a cut-size associated with the first single node is less than or equal to one of the sizes of lookup tables, the one size is selected to implement the first single node. If a lookup table size was not selected for the first single node, the node and its predecessor nodes are selectively collapsed into a second single node as a function of the delay factors and the maximum delay factor increased by a selected value. If a cut-size associated with the second single nodes is less than or equal to one of the sizes of lookup tables, the one size is selected to implement the second single node.

    摘要翻译： 用于将逻辑节点映射到可编程门阵列中的多个查找表大小的过程。 作为与多个查找表的大小相关联的延迟因子和与先前节点相关联的最大延迟因子的函数，节点及其前导节点被选择性地折叠成第一单个节点。 如果与第一单个节点相关联的剪切尺寸小于或等于查找表的大小之一，则选择一个大小来实现第一个单个节点。 如果没有为第一个单个节点选择查找表大小，则根据延迟因子和最大延迟因子增加选定值，节点及其前导节点选择性地折叠成第二个单个节点。 如果与第二单个节点相关联的剪切尺寸小于或等于查找表的大小之一，则选择一个大小来实现第二个单个节点。

    Configurable logic element with ability to evaluate five and six input functions
    9.
    发明授权
    Configurable logic element with ability to evaluate five and six input functions 失效
    可配置逻辑元件，具有评估五个和六个输入功能的能力

    公开(公告)号：US5920202A

    公开(公告)日：1999-07-06

    申请号：US835088

    申请日：1997-04-04

    申请人： Steven P. Young ,  Shekhar Bapat ,  Kamal Chaudhary ,  Trevor J. Bauer ,  Roman Iwanczuk

    发明人： Steven P. Young ,  Shekhar Bapat ,  Kamal Chaudhary ,  Trevor J. Bauer ,  Roman Iwanczuk

    IPC分类号： H01L25/00 ,  H03K19/173 ,  H03K19/177 ,  G06F7/38

    CPC分类号： H03K19/17728 ,  H03K19/1737 ,  H03K19/17704

    摘要： The invention provides a Configurable Logic Element (CLE) preferably included in each of an array of identical tiles. A CLE according to the invention has four function generators. The outputs of two function generators are combined with a fifth independent input in a five-input-function multiplexer or function generator to produce an output that can be any function of five inputs, or some functions of up to nine inputs. The outputs of the other two function generators are similarly combined. The outputs of the two five-input-function multiplexers or function generators are then combined with a sixth independent input in a first six-input-function multiplexer or function generator, and with a different sixth independent input in a second six-input-function multiplexer or function generator. The two six-input-function multiplexers or function generators therefore produce two outputs of which one can be any function of six inputs; the other output can be any function of six inputs provided that five inputs are shared between the two 6-input functions. Some functions of up to nineteen inputs can also be generated in a single CLE.

    摘要翻译： 本发明提供了优选地包括在相同瓦片的阵列中的每一个中的可配置逻辑元件（CLE）。 根据本发明的CLE具有四个功能发生器。 两个功能发生器的输出与五输入功能多路复用器或函数发生器中的第五个独立输入组合，以产生可以是五个输入或多达九个输入的一些功能的输出。 其他两个功能发生器的输出类似地组合。 然后，两个五输入功能多路复用器或函数发生器的输出与第六个六输入函数多路复用器或函数发生器中的第六个独立输入组合，并在第六个六输入函数中与不同的第六独立输入进行组合 多路复用器或函数发生器。 因此，两个六输入功能多路复用器或函数发生器产生两个输出，其中一个可以是六个输入的任何功能; 另外的输出可以是六个输入的任何功能，只要在两个6输入功能之间共享五个输入。 也可以在单个CLE中生成多达十九个输入的某些功能。

    FPGA repeatable interconnect structure with hierarchical interconnect lines
    10.
    发明授权
    FPGA repeatable interconnect structure with hierarchical interconnect lines 失效
    具有分层互连线路的FPGA可重复互连结构

    公开(公告)号：US5914616A

    公开(公告)日：1999-06-22

    申请号：US806997

    申请日：1997-02-26

    申请人： Steven P. Young ,  Kamal Chaudhary ,  Trevor J. Bauer

    发明人： Steven P. Young ,  Kamal Chaudhary ,  Trevor J. Bauer

    IPC分类号： H01L25/00 ,  H03K19/173 ,  H03K19/177

    CPC分类号： H03K19/17796 ,  H03K19/1737 ,  H03K19/17704

    摘要： The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. A combination of single-length lines connecting to adjacent tiles and intermediate-length lines connecting to tiles several tiles away creates an interconnect hierarchy which allows any logic block to be connected to any other logic block, yet also allows for fast paths to both adjacent tiles and tiles some distance away. Longer interconnect lines may be included as a third level of hierarchy to permit interconnection of widely separated tiles. In a preferred embodiment, from a given tile an intermediate-length line connects to the tile three tiles away, then continues and connects to the tile six tiles away. In this embodiment, the intermediate-length line does not connect to the intervening tiles one, two, four, and five tiles away.

    摘要翻译： 本发明提供了优选地包括在相同瓦片阵列中的FPGA互连结构。 连接到相邻瓦片的单条线和连接到瓦片几个瓦片的中间线的组合创建互连层级，其允许任何逻辑块连接到任何其他逻辑块，但是也允许到相邻瓦片的快速路径 和瓷砖有一段距离。 可以将更长的互连线包括为第三层次以允许广泛分隔的瓷砖的互连。 在优选实施例中，从给定的瓦片中，中间线连接到瓦片三瓦片，然后继续并连接到瓦片六瓦片。 在该实施例中，中间长度线不连接到中间瓦片一个，两个，四个和五个瓦片。