Decoder for trellis encoded interleaved data stream and HDTV receiver
including such a decoder
    1.
    发明授权
    Decoder for trellis encoded interleaved data stream and HDTV receiver including such a decoder 失效
    用于网格编码交织数据流的解码器和包括这样的解码器的HDTV接收机

    公开(公告)号:US6141384A

    公开(公告)日:2000-10-31

    申请号:US800637

    申请日:1997-02-14

    摘要: In the standard format now adapted by FCC for a digital HDTV signal, the video data symbols are interleaved and trellis encoded in accordance with a 4-state trellis code and the interleaving is of sequences of every 12 successive symbols. At the receiver the trellis decoder is therefore projected to consist of 12 respective decoder stages for the 12 interleaved sequences, each decoder stage having a branch metric calculator unit (BMC), an add-compare-select (ACS) unit and a path memory unit (PMU). The present invention separates the path memory requirements for the 12 interleaved sequences from the requisite BMC and ACS functions, so that the latter two units can provide those functions for all of the 12 interleaved sequences. A single extended PMU provides for storage of pointers to possible predecessor states of the trellis code corresponding to a present state thereof, going back to a predetermined number (such as 16) of sequentially preceding received symbol values. The PMU also provides, in each of the storage stages, sequential storage elements corresponding to the sequential interleaved symbol values. This makes it possible for the PMU to be realized as a single integrated RAM by appropriate grouping of the trellis code states. Also, the ACS function is performed by two separate ACS units for two mutually independent groups of trellis code states.

    摘要翻译: 在现在由FCC适用于数字HDTV信号的标准格式中,视频数据符号根据4状态网格码进行交织和格网编码,并且交织是每12个连续符号的序列。 因此,在接收机处,网格解码器被投射为12个交错序列的12个相应的解码器级,每个解码器级具有分支度量计算器单元(BMC),加法比较选择(ACS)单元和路径存储器单元 (PMU)。 本发明将12个交错序列的路径存储器要求与必要的BMC和ACS功能分离,使得后两个单元可以为12个交错序列中的全部提供那些功能。 单个扩展PMU提供用于存储指向与其当前状态相对应的格状码的可能的先前状态的指针,返回到先前接收的符号值的预定数量(例如16)。 PMU还在每个存储级中提供与顺序交织的符号值相对应的顺序存储元件。 这使得PMU可以通过适当地分组格状态来实现为单个集成RAM。 此外,ACS功能由两个独立的ACS单元执行,用于两个相互独立的网格码状态组。

    Free-running numerically-controlled oscillator using complex multiplication with compensation for amplitude variation due to cumulative round-off errors
    2.
    发明授权
    Free-running numerically-controlled oscillator using complex multiplication with compensation for amplitude variation due to cumulative round-off errors 有权
    自由运行的数控振荡器使用复数乘法,由于累积舍入误差导致的幅度变化补偿

    公开(公告)号:US07707235B2

    公开(公告)日:2010-04-27

    申请号:US10586915

    申请日:2005-01-25

    IPC分类号: G06F1/02

    CPC分类号: H03B28/00 G06G7/26

    摘要: A method and apparatus for efficiently generating complex sinusoids of a desired frequency by multiplying a phasor by a predetermined value once every sampling interval, and using the highest order bits within the phasor to identify if the phasor is at an integer multiple 45 degrees and substituting components in the phasor if it is determined that the phasor is an integer multiple of 45 degrees. If the phasor is not identified as being an integer multiple of 45 degrees then an error factor for both the real and imaginary components is determined and the real and imaginary components are corrected by removing the error factor.

    摘要翻译: 一种用于通过将相量乘以预定值一次每个采样间隔并且使用相量内的最高阶位来识别相量是否处于整数倍45度并且代替分量的方法和装置,用于有效地产生所需频率的复数正弦曲线 如果确定相量是45度的整数倍,则在相量中。 如果相量不被确定为45度的整数倍,则确定实部和虚部的误差因子,并通过去除误差因子来校正实部和虚部。