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1.发明授权Data merge unit, a method of producing an interleaved data stream, a network analyser and a method of analysing a network 有权数据合并单元，交织数据流的生成方法，网络分析器以及分析网络的方法公开(公告)号：US07711006B2
公开(公告)日：2010-05-04
申请号：US10564731
申请日：2004-08-13
IPC分类号： H04J3/24
CPC分类号： H04L47/10 , H04J3/247 , H04L47/22 , H04L49/90 , H04L49/9094
摘要： A data merge unit is provided for providing an interleaved data stream, the data stream including data frames received on two or more input channels, wherein data frames from each of the two or more input channels are arranged in time-slots of the interleaved data stream. The data merge unit comprises an input unit to receive data frames from two or more input channels, a frame merge buffer arranged to receive data frames from the two or more input channels via the input unit and store said data frames; and, an output generator to generate the interleaved data stream, the output generator being configured to select complete data frames from the frame merge buffer and arrange said complete data frames in the interleaved data stream.
摘要翻译： 提供数据合并单元，用于提供交错数据流，所述数据流包括在两个或多个输入通道上接收的数据帧，其中来自两个或更多个输入通道中的每一个的数据帧被布置在交错数据流的时隙中 。 该数据合并单元包括：一个输入单元，用于从两个或多个输入通道接收数据帧;帧合并缓冲器，被布置成经由输入单元从两个或多个输入通道接收数据帧，并存储所述数据帧; 以及输出生成器，用于生成交错数据流，所述输出生成器被配置为从所述帧合并缓冲器中选择完整数据帧，并且将所述完整数据帧排列在所述交错数据流中。
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公开(公告)号：US06892287B1
公开(公告)日：2005-05-10
申请号：US10209490
申请日：2002-07-31
CPC分类号： H04L12/5601 , H04L49/552 , H04L2012/5628 , H04L2012/5652
摘要： A method and system for partial reassembly of data frames reconstructed from data cells received from a network data stream includes partially reassembling the header cells and the last cell of each frame and passing the remainder of data frame cells to a capture buffer in an unassembled state. Since the partially reassembled data frames include only a subset of each frame, they can be processed at the full line-rate of the network data stream without causing an overflow. The cells in the partially reassembled frames are only those cells required for functions that must be performed at the full line rate.
摘要翻译： 用于从从网络数据流接收的数据单元重构的数据帧的部分重组的方法和系统包括部分地重新组合每个帧的标题单元和最后一个单元，并将剩余的数据帧单元传送到处于未组装状态的捕获缓冲器。 由于部分重新组装的数据帧仅包括每个帧的子集，所以它们可以以网络数据流的全线速率被处理，而不会引起溢出。 部分重新组装的帧中的单元只是必须以全线速率执行的功能所需的单元。
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公开(公告)号：US5537650A
公开(公告)日：1996-07-16
申请号：US232536
申请日：1992-12-14
CPC分类号： G06F1/3218 , G09G3/3611 , G09G5/395 , G09G2330/021
摘要： Video subsystem power savings are achieved by shutting off power to unused subcircuits during blanking. Digital circuitry within the video subsystem not used during blanking is shut-down by turning off the clock thereto. Analog circuitry within a digital to analog converter is shut-down by turning off the constant current reference thereto. A functional unit containing digital circuitry within a serializer palette digital to analog converter (SPDAC) is shut-down by turning off the clock thereto during system operation in a mode where the functional unit is not utilized. A computer system having a monochrome display saves power by shutting off DAC digital circuitry clocks and DAC analog circuitry constant current references of all DACs but one. A portable computer with a liquid crystal display (LCD), a SPDAC for driving an external display and a LCD controller, saves power by shutting down video subsystem functional units and analog DAC circuitry not used for driving the LCD. Digital circuitry within the LCD controller is shut-down when an external display is being driven. In a portable computer operating in a SUSPEND state, video subsystem functional units are shut-down.
摘要翻译： 通过在消隐期间关闭未使用的子电路的电源来实现视频子系统的功率节省。 在消隐期间未使用的视频子系统内的数字电路通过关闭时钟来关闭。 通过关闭数模转换器的恒定电流基准来关闭数模转换器中的模拟电路。 在串行器调色板数模转换器（SPDAC）中包含数字电路的功能单元在不使用功能单元的模式下在系统操作期间关闭时钟来关闭。 具有单色显示器的计算机系统通过关闭所有DAC的DAC数字电路时钟和DAC模拟电路恒定电流基准来节省功率，但一个。 具有液晶显示器（LCD）的便携式计算机，用于驱动外部显示器的SPDAC和LCD控制器，通过关闭不用于驱动LCD的视频子系统功能单元和模拟DAC电路来节省电力。 当外部显示器被驱动时，LCD控制器内的数字电路被关闭。 在SUSPEND状态下运行的便携式计算机中，视频子系统功能单元被关闭。
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4.发明授权Direct memory access controller and method of filtering data during data transfer from a source memory to a destination memory 失效直接存储器访问控制器和在从源存储器到目的地存储器的数据传输期间过滤数据的方法公开(公告)号：US06904473B1
公开(公告)日：2005-06-07
申请号：US10209572
申请日：2002-07-31
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , Y10S707/99933 , Y10S707/99936
摘要： A direct memory access controller includes a source memory controller for controlling a source memory, a destination bus controller for controlling the transfer of data to a destination memory, a first-in-first-out memory buffer for receiving data from the source memory, and a filter connected upstream of the first-in-first-out memory buffer for comparing the source memory data to a filter criterion and passing to the first-in-first-out memory buffer only that data which matches the filter criterion.
摘要翻译： 直接存储器访问控制器包括用于控制源存储器的源存储器控制器，用于控制到目的地存储器的数据传送的目的地总线控制器，用于从源存储器接收数据的先进先出存储器缓冲器，以及 连接在先进先出存储器缓冲器的上游的过滤器，用于将源存储器数据与过滤器标准进行比较，并将仅与先前先出存储器缓冲器的数据传送到与过滤器标准相匹配的数据。
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