公开(公告)号：US20110096447A1

公开(公告)日：2011-04-28

申请号：US12905328

申请日：2010-10-15

申请人： Teppei HIGUCHI ,  Katsuhiko MAKI

发明人： Teppei HIGUCHI ,  Katsuhiko MAKI

IPC分类号： H02H9/04

CPC分类号： H01L27/0255

摘要： An integrated circuit device includes: a pad to which a signal is input; an analog circuit performing analog processing of the signal input via the pad; and a capacitor disposed between a signal input node of the analog circuit and the pad, wherein the pad and one end of the capacitor are connected to each other with a pad wiring formed of an uppermost metal layer.

摘要翻译： 集成电路装置包括：输入信号的焊盘; 模拟电路，经由所述焊盘进行信号输入的模拟处理; 以及设置在所述模拟电路的信号输入节点和所述焊盘之间的电容器，其中所述焊盘和所述电容器的一端通过由最上层金属层形成的焊盘布线彼此连接。

公开(公告)号：US20070290752A1

公开(公告)日：2007-12-20

申请号：US11891844

申请日：2007-08-13

申请人： Katsuhiko Maki

发明人： Katsuhiko Maki

IPC分类号： H03F3/45

CPC分类号： G09G3/3688 ,  H03K5/023 ,  H03K19/018578

摘要： An arithmetic amplifying circuit for driving a capacitive load is provided including a voltage follower circuit converting an input signal to impedance, and a resistance circuit which is serially connected between the voltage follower circuit and an output of the arithmetic amplifying circuit. The voltage follower circuit includes a differential section, which amplifies a differential between the input signal and the output signal of the voltage follower circuit, and an output section, which outputs the output signal of the voltage follower circuit based on an output of the differential section, and drives a capacitive load via the resistance circuit.

摘要翻译： 提供一种用于驱动电容性负载的运算放大电路，包括将输入信号转换为阻抗的电压跟随器电路，以及串联连接在电压跟随器电路和运算放大电路的输出端之间的电阻电路。 电压跟随器电路包括放大输入信号和电压跟随器电路的输出信号之间的差分的差分部分和输出部分，该输出部分基于差分部分的输出输出电压跟随器电路的输出信号 并通过电阻电路驱动电容性负载。

公开(公告)号：US20070001973A1

公开(公告)日：2007-01-04

申请号：US11270632

申请日：2005-11-10

申请人： Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa ,  Satoru Ito ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira ,  Katsuhiko Maki

发明人： Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa ,  Satoru Ito ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira ,  Katsuhiko Maki

IPC分类号： G09G3/36

CPC分类号： G09G3/3611 ,  G09G3/3688 ,  G09G3/3696 ,  G09G2360/18

摘要： An integrated circuit device including first to Nth circuit blocks CB1 to CBN disposed along a first direction D1, when the first direction D1 is a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction D2 is a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CB1 to CBN include a logic circuit block LB, a grayscale voltage generation circuit block GB, data driver blocks DB1 to DB4, and a power supply circuit block PB. The data driver blocks DB1 to DB4 are disposed between the logic circuit block LB and the grayscale voltage generation circuit block GB, and the power supply circuit block PB.

摘要翻译： 一种集成电路装置，包括沿着第一方向D 1布置的第一至第N电路块CB 1至CBN，当第一方向D 1是从集成电路器件的第一侧朝向与第一方向相反的第三侧的方向时 所述第一侧为短边，当第二方向D 2为从所述集成电路器件的第二侧朝向与所述第二侧相反的第四侧的方向时，所述第二侧为长边。 电路块CB 1至CBN包括逻辑电路块LB，灰度电压产生电路块GB，数据驱动器块DB 1至DB 4和电源电路块PB。 数据驱动器块DB 1至DB 4设置在逻辑电路块LB和灰度级电压产生电路块GB之间，以及电源电路块PB。

公开(公告)号：US07034797B2

公开(公告)日：2006-04-25

申请号：US10455652

申请日：2003-06-05

申请人： Katsuhiko Maki

发明人： Katsuhiko Maki

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G2310/027 ,  G09G2310/0297 ,  G09G2330/021

摘要： A drive circuit is provided that can drive a display panel with low power consumption, and an electro optical device including the drive circuit and its drive method are included. Switching signals RSEL, GSEL, and BSEL for demultiplexing are produced so as to control turning switching elements DSWR, DSWG, and DSWB for demultiplexing on and off, which separate data signal where R, G, and B are multiplexed and transmitted. An overlapped period, for periods of activating RSEL, GSEL, and BSEL is set between the timing of changing polarity of common voltage and the timing of assuring writing data signal to a pixel electrode. A drive circuit includes a reference voltage production circuit and a digital to analog conversion circuit and an output circuit, which outputs a programmed voltage (a reference voltage having the same phase as the common voltage) during the overlapped period. The first reference voltage production circuit includes plurality of operational amplifiers and the first and second voltage division circuits.

摘要翻译： 提供了能够以低功耗驱动显示面板的驱动电路，并且包括包括驱动电路及其驱动方法的电光装置。 产生用于解复用的开关信号RSEL，GSEL和BSEL，以便控制转换开关元件DSWR，DSWG和DSWB用于多路分解导通和关断，分离数据信号，其中R，G和B被复用和发送。 在改变公共电压的极性的定时和确保将数据信号写入像素电极的定时之间，设置激活RSEL，GSEL和BSEL的周期。 驱动电路包括参考电压产生电路和数模转换电路和输出电路，其在重叠周期期间输出编程电压（与公共电压具有相同相位的参考电压）。 第一参考电压产生电路包括多个运算放大器和第一和第二分压电路。

公开(公告)号：US20060044248A1

公开(公告)日：2006-03-02

申请号：US11175954

申请日：2005-07-06

申请人： Katsuhiko Maki

发明人： Katsuhiko Maki

IPC分类号： G09G3/36

CPC分类号： G09G3/3614 ,  G09G3/3655 ,  G09G3/3688 ,  G09G3/3696 ,  G09G2310/02 ,  G09G2310/027 ,  G09G2320/0233

摘要： A display panel driving circuit including: a memory temporarily storing input image data; a controller controlling reading operation of the image data for each line from the memory in order that a line number for starting display is changed every predetermined number of a frame period on a display panel; and an image signal supplying unit converting the image data for each line, which are sequentially read out from the memory, into a plurality of analog image signals and supplying the image signals to the display panel.

摘要翻译： 一种显示面板驱动电路，包括：临时存储输入图像数据的存储器; 控制器控制来自存储器的每行的图像数据的读取操作，以便在显示面板上每隔预定数量的帧周期改变开始显示的行号; 以及将从存储器顺序读出的每行的图像数据转换为多个模拟图像信号并将图像信号提供给显示面板的图像信号提供单元。

公开(公告)号：US06753731B2

公开(公告)日：2004-06-22

申请号：US10356353

申请日：2003-01-30

申请人： Katsuhiko Maki

发明人： Katsuhiko Maki

IPC分类号： H03F345

CPC分类号： H03F3/3023 ,  H03F1/0261 ,  H03F3/45183

摘要： An operational amplifier circuit includes a differential section, an output section having drive transistors PT15 and NT15, a voltage setting circuit which sets a programming voltage at a node N1, and a capacitance element C1. The programming voltage is set to the node N1, and then a change in voltage at an output node NQ1 of the differential section is transferred to the node N1 by the capacitance element C1. Switching elements SW1 and SW2 are turned off before the programming voltage is set to the node N1, and are turned on after the setting. A switching element SW4 is turned on and the node N1 is set to VSS, and subsequently the node N1 is set to the programming voltage (VDD−VTH) by turning on the switching element SW3. The programming voltage is set in a switching period between scan periods.

摘要翻译： 运算放大器电路包括差分部分，具有驱动晶体管PT15和NT15的输出部分，设置节点N1处的编程电压的电压设置电路和电容元件C1。 编程电压被设定为节点N1，然后通过电容元件C1将差分部分的输出节点NQ1的电压变化传送到节点N1。 开关元件SW1和SW2在编程电压被设置到节点N1之前被断开，并且在设置之后被接通。 开关元件SW4导通，节点N1设定为VSS，通过接通开关元件SW3，将节点N1设定为编程电压（VDD-VTH）。 编程电压设置在扫描周期之间的切换周期内。

公开(公告)号：US07646371B2

公开(公告)日：2010-01-12

申请号：US11436038

申请日：2006-05-18

申请人： Katsuhiko Maki

发明人： Katsuhiko Maki

IPC分类号： G09G3/36 ,  G09G5/00 ,  H04N3/02

CPC分类号： G09G3/3688 ,  G09G3/3696 ,  G09G2310/027 ,  G09G2330/02 ,  G09G2330/021 ,  G09G2360/16

摘要： A driver circuit includes an operational amplifier OPC1 which drives a data line by a rail-to-rail operation or a non-rail-to-rail operation based on a grayscale voltage corresponding to one of first to Pth (P is an integer of four or more) grayscale values, and an operational amplifier control section OPCC1 which causes the operational amplifier OPC1 to perform the rail-to-rail operation or the non-rail-to-rail operation based on grayscale data. When the sth (1≦s≦P, s is an integer) grayscale value corresponding to the grayscale data is in a range of the qth (1

摘要翻译： 驱动器电路包括：运算放大器OPC1，其基于与第一至第P中的一个相对应的灰度电压，通过轨到轨操作或非轨到轨操作来驱动数据线（P为整数四 或更多）灰度值，以及运算放大器控制部分OPCC1，其使得运算放大器OPC1基于灰度数据执行轨到轨操作或非轨到轨操作。 当与灰度级数据对应的sth（1 <= s <= P，s为整数）灰度级值在q（1

公开(公告)号：US20080150866A1

公开(公告)日：2008-06-26

申请号：US11987252

申请日：2007-11-28

申请人： Katsuhiko Maki

发明人： Katsuhiko Maki

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/3696 ,  G09G2310/027 ,  G09G2310/0291

摘要： A source driver that drives a plurality of source lines of an electro-optical device includes a grayscale voltage generation circuit that outputs first and second grayscale voltages corresponding to grayscale data, and a source line driver circuit that drives a source line among the plurality of source lines based on the first and second grayscale voltages. The source line driver circuit includes a flip-around sample/hold circuit that outputs an output grayscale voltage between the first and second grayscale voltages to the source line.

摘要翻译： 驱动电光装置的多条源极线的源极驱动器包括输出对应于灰阶数据的第一和第二灰度电压的灰阶电压产生电路，以及驱动多个源极之间的源极线的源极线驱动电路 基于第一和第二灰度电压的线。 源极线驱动器电路包括翻转采样/保持电路，其将第一和第二灰度级电压之间的输出灰度电压输出到源极线。

公开(公告)号：US20070002063A1

公开(公告)日：2007-01-04

申请号：US11270551

申请日：2005-11-10

申请人： Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa ,  Satoru Ito ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira ,  Katsuhiko Maki

发明人： Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa ,  Satoru Ito ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira ,  Katsuhiko Maki

IPC分类号： G09G5/37

CPC分类号： G09G3/3688 ,  G09G2310/0267 ,  G09G2310/027

摘要： An integrated circuit device including first to Nth circuit blocks CB1 to CBN disposed along a first direction D1, when the first direction D1 is a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction D2 is a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CB1 to CBN include at least one memory block MB which stores image data, and at least one data driver block DB which drives data lines. The memory block MB and the data driver block DB are disposed adjacent to each other along the first direction D1.

摘要翻译： 一种集成电路装置，包括沿着第一方向D 1布置的第一至第N电路块CB 1至CBN，当第一方向D 1是从集成电路器件的第一侧朝向与第一方向相反的第三侧的方向时 所述第一侧为短边，当第二方向D 2为从所述集成电路器件的第二侧朝向与所述第二侧相反的第四侧的方向时，所述第二侧为长边。 电路块CB 1至CBN包括存储图像数据的至少一个存储器块MB和驱动数据线的至少一个数据驱动器块DB。 存储块MB和数据驱动块DB沿着第一方向D1彼此相邻设置。

公开(公告)号：US20060284806A1

公开(公告)日：2006-12-21

申请号：US11436038

申请日：2006-05-18

申请人： Katsuhiko Maki

发明人： Katsuhiko Maki

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/3696 ,  G09G2310/027 ,  G09G2330/02 ,  G09G2330/021 ,  G09G2360/16

摘要： A driver circuit includes an operational amplifier OPC1 which drives a data line by a rail-to-rail operation or a non-rail-to-rail operation based on a grayscale voltage corresponding to one of first to Pth (P is an integer of four or more) grayscale values, and an operational amplifier control section OPCC1 which causes the operational amplifier OPC1 to perform the rail-to-rail operation or the non-rail-to-rail operation based on grayscale data. When the sth (1≦s≦P, s is an integer) grayscale value corresponding to the grayscale data is in a range of the qth (1

摘要翻译： 驱动器电路包括运算放大器OPC 1，其通过轨到轨操作或非轨到轨操作来驱动数据线，该运算放大器基于与第一至第 Pth（P是四个或更多个的整数）灰度值，以及使运算放大器OPC 1执行轨至轨的运算放大器控制部分OPCC1 < 基于灰度数据的轨道操作或非轨到轨操作。 当与灰度级数据对应的sth（1 <= s <= P，s为整数）灰度级值在q（1 基于与sth灰度值对应的灰度电压，通过非轨到轨操作来驱动数据线， 当灰度级灰度值不在第q至第r灰度值的范围内时，运算放大器OPC 1 通过轨到轨操作基于对应于 sth灰度值。