公开(公告)号：US08307143B2

公开(公告)日：2012-11-06

申请号：US12771072

申请日：2010-04-30

申请人： Katsuhiro Hirayama ,  Hiroto Yoshikawa ,  Yoshihiro Ueda ,  Osamu Mikami

发明人： Katsuhiro Hirayama ,  Hiroto Yoshikawa ,  Yoshihiro Ueda ,  Osamu Mikami

IPC分类号： G06F13/20 ,  G06F13/40

CPC分类号： G06F13/385 ,  G06F2213/3804

摘要： There is provided an interface card system for SD bus control. The interface card system for SD bus control includes a CPU bus interface 11a and/or an SD bus interface 11b, a host interface module 16 connected to the interfaces which interprets an SD command and controls operation of the whole of the interface card system, first and second internal SD host engines 15a and 15b which function as a host controller, first and second selectors 14a and 14b respectively connected to the internal SD host engines which each select a path for data or a command, first and second SD bus interfaces 13a and 13b respectively connected to the selectors, and a data pass-through control section 17 connected to the SD bus interfaces connected to the selectors which allows an SD command and data to pass through.

摘要翻译： 提供了一种用于SD总线控制的接口卡系统。 用于SD总线控制的接口卡系统包括CPU总线接口11a和/或SD总线接口11b，连接到解释SD命令并控制整个接口卡系统的操作的接口的主机接口模块16 和用作主机控制器的第二内部SD主机引擎15a和15b，分别连接到内部SD主机引擎的第一和第二选择器14a和14b，每个内部SD主机引擎选择数据或命令的路径，第一和第二SD总线接口13a和 13b，以及连接到连接到选择器的SD总线接口的数据传递控制部分17，其允许SD命令和数据通过。

公开(公告)号：US20110238880A1

公开(公告)日：2011-09-29

申请号：US12771072

申请日：2010-04-30

申请人： Katsuhiro Hirayama ,  Hiroto Yoshikawa ,  Yoshihiro Ueda ,  Osamu Mikami

发明人： Katsuhiro Hirayama ,  Hiroto Yoshikawa ,  Yoshihiro Ueda ,  Osamu Mikami

IPC分类号： G06F13/00 ,  G06F13/28

CPC分类号： G06F13/385 ,  G06F2213/3804

摘要： There is provided an interface card system for SD bus control. The interface card system for SD bus control includes a CPU bus interface 11a and/or an SD bus interface 11b, a host interface module 16 connected to the interfaces which interprets an SD command and controls operation of the whole of the interface card system, first and second internal SD host engines 15a and 15b which function as a host controller, first and second selectors 14a and 14b respectively connected to the internal SD host engines which each select a path for data or a command, first and second SD bus interfaces 13a and 13b respectively connected to the selectors, and a data pass-through control section 17 connected to the SD bus interfaces connected to the selectors which allows an SD command and data to pass through.

摘要翻译： 提供了一种用于SD总线控制的接口卡系统。 用于SD总线控制的接口卡系统包括CPU总线接口11a和/或SD总线接口11b，连接到解释SD命令并控制整个接口卡系统的操作的接口的主机接口模块16 和用作主机控制器的第二内部SD主机引擎15a和15b，分别连接到内部SD主机引擎的第一和第二选择器14a和14b，每个内部SD主机引擎选择数据或命令的路径，第一和第二SD总线接口13a和 13b，以及连接到连接到选择器的SD总线接口的数据传递控制部分17，其允许SD命令和数据通过。

公开(公告)号：US5974578A

公开(公告)日：1999-10-26

申请号：US906260

申请日：1997-08-05

申请人： Takashi Mizokawa ,  Katsuhiro Hirayama

发明人： Takashi Mizokawa ,  Katsuhiro Hirayama

IPC分类号： G01R31/3167 ,  G01R31/28

CPC分类号： G01R31/3167

摘要： In a mixed signal integrated circuit containing both an analog core circuit and a digital core circuit, a plurality of dedicated analog boundary scan cells disposed around the analog core circuit are connected in series by a dedicated analog boundary scan path. A plurality of dedicated digital boundary scan cells disposed around a digital core circuit are connected in series by a dedicated digital boundary scan path. The analog and digital boundary scan paths are independent of each other. In testing the analog or digital core circuit, the boundary scan path dedicated thereto is selected so that sets of test control data or test data are shifted only in the boundary scan cells dedicated thereto. As a consequence, a test pattern is shortened and the analog or digital core circuit can efficiently be tested in a shorter period of time.

摘要翻译： 在包含模拟核心电路和数字核心电路的混合信号集成电路中，设置在模拟核心电路周围的多个专用模拟边界扫描单元通过专用模拟边界扫描路径串联连接。 设置在数字核心电路周围的多个专用数字边界扫描单元通过专用数字边界扫描路径串联连接。 模拟和数字边界扫描路径彼此独立。 在测试模拟或数字核心电路时，选择专用于其的边界扫描路径，使得仅在专用于其的边界扫描单元中移动测试控制数据或测试数据的集合。 因此，测试模式缩短，并且模拟或数字核心电路可以在更短的时间内有效地测试。

公开(公告)号：US07225357B2

公开(公告)日：2007-05-29

申请号：US10759213

申请日：2004-01-20

申请人： Ping Huei Tai ,  Katsuhiro Hirayama

发明人： Ping Huei Tai ,  Katsuhiro Hirayama

IPC分类号： G06F11/00

CPC分类号： G06F11/2221

摘要： An SDIO card development supporting system for development of SDIO cards, an SDIO controller reference board, and a method for running the system are disclosed. The SDIO card development supporting system includes: (a) a hardware component comprising: (i) a platform equipped with an operating system and a memory operably connected to the operating system; (ii) an SD host board including an SDIO host device; and (iii) an SD bus operably connecting the operating system of the platform to the SD host board; and (b) a software component stored in the memory of the platform, wherein the software component comprises an SDIO test program that runs on the operating system of the platform.

摘要翻译： 公开了一种用于开发SDIO卡的SDIO卡开发支持系统，SDIO控制器参考板以及用于运行该系统的方法。 SDIO卡开发支持系统包括：（a）硬件组件，包括：（i）具有可操作地连接到操作系统的操作系统和存储器的平台; （ii）包括SDIO主机设备的SD主机板; 和（iii）可操作地将平台的操作系统连接到SD主机板的SD总线; 和（b）存储在所述平台的存储器中的软件组件，其中所述软件组件包括在所述平台的操作系统上运行的SDIO测试程序。