-
公开(公告)号：US20110238880A1
公开(公告)日：2011-09-29
申请号：US12771072
申请日：2010-04-30
CPC分类号： G06F13/385 , G06F2213/3804
摘要： There is provided an interface card system for SD bus control. The interface card system for SD bus control includes a CPU bus interface 11a and/or an SD bus interface 11b, a host interface module 16 connected to the interfaces which interprets an SD command and controls operation of the whole of the interface card system, first and second internal SD host engines 15a and 15b which function as a host controller, first and second selectors 14a and 14b respectively connected to the internal SD host engines which each select a path for data or a command, first and second SD bus interfaces 13a and 13b respectively connected to the selectors, and a data pass-through control section 17 connected to the SD bus interfaces connected to the selectors which allows an SD command and data to pass through.
摘要翻译： 提供了一种用于SD总线控制的接口卡系统。 用于SD总线控制的接口卡系统包括CPU总线接口11a和/或SD总线接口11b，连接到解释SD命令并控制整个接口卡系统的操作的接口的主机接口模块16 和用作主机控制器的第二内部SD主机引擎15a和15b，分别连接到内部SD主机引擎的第一和第二选择器14a和14b，每个内部SD主机引擎选择数据或命令的路径，第一和第二SD总线接口13a和 13b，以及连接到连接到选择器的SD总线接口的数据传递控制部分17，其允许SD命令和数据通过。
-
公开(公告)号：US08307143B2
公开(公告)日：2012-11-06
申请号：US12771072
申请日：2010-04-30
CPC分类号： G06F13/385 , G06F2213/3804
摘要： There is provided an interface card system for SD bus control. The interface card system for SD bus control includes a CPU bus interface 11a and/or an SD bus interface 11b, a host interface module 16 connected to the interfaces which interprets an SD command and controls operation of the whole of the interface card system, first and second internal SD host engines 15a and 15b which function as a host controller, first and second selectors 14a and 14b respectively connected to the internal SD host engines which each select a path for data or a command, first and second SD bus interfaces 13a and 13b respectively connected to the selectors, and a data pass-through control section 17 connected to the SD bus interfaces connected to the selectors which allows an SD command and data to pass through.
摘要翻译： 提供了一种用于SD总线控制的接口卡系统。 用于SD总线控制的接口卡系统包括CPU总线接口11a和/或SD总线接口11b，连接到解释SD命令并控制整个接口卡系统的操作的接口的主机接口模块16 和用作主机控制器的第二内部SD主机引擎15a和15b，分别连接到内部SD主机引擎的第一和第二选择器14a和14b，每个内部SD主机引擎选择数据或命令的路径，第一和第二SD总线接口13a和 13b，以及连接到连接到选择器的SD总线接口的数据传递控制部分17，其允许SD命令和数据通过。
-
3.发明授权Method and apparatus for compression of universal serial bus data transmission 失效用于压缩通用串行总线数据传输的方法和装置公开(公告)号：US06529988B1
公开(公告)日：2003-03-04
申请号：US09430668
申请日：1999-10-28
申请人： Hiroto Yoshikawa , Masakazu Urade
发明人： Hiroto Yoshikawa , Masakazu Urade
IPC分类号： G06F1300
CPC分类号： G06F13/4027
摘要： Disclosed is an apparatus and method for transferring data from a directly from peripheral computer device to a computer via a universal serial bus. The disclosed method and apparatus can also compress the transferred data. The apparatus can include a Serial Interface Engine (SIE) connected with the computer and having a latch and a First-In-First-Out memory (FIFO) connected to the latch of the SIE. The FIFO temporarily stores data from the peripheral computer device and transfers the data to the latch of the SIE. A read input of the latch is driven at a first clock frequency and an output of the FIFO is driven at a second clock frequency. The second clock frequency is at least intermittently higher than the first clock frequency. Thus, a portion of the data placed on the output of the FIFO at the second clock frequency is not read into the latch. This allows data to be compressed as it is transferred from the FIFO to the SIE.
摘要翻译： 公开了一种用于通过通用串行总线将数据从外围计算机设备直接传送到计算机的装置和方法。 所公开的方法和装置还可以压缩传送的数据。 该装置可以包括与计算机连接并具有连接到SIE的锁存器的锁存器和先进先出存储器（FIFO）的串行接口引擎（SIE）。 FIFO临时存储来自外围计算机设备的数据，并将数据传送到SIE的锁存器。 锁存器的读取输入以第一时钟频率被驱动，FIFO的输出以第二时钟频率被驱动。 第二时钟频率至少间歇地高于第一时钟频率。 因此，以第二时钟频率放置在FIFO的输出上的数据的一部分不被读入锁存器。 这样就可以在数据从FIFO传输到SIE时进行压缩。
-
公开(公告)号：US07856527B2
公开(公告)日：2010-12-21
申请号：US11859411
申请日：2007-09-21
申请人： Hiroto Yoshikawa
发明人： Hiroto Yoshikawa
IPC分类号： G06F13/00
CPC分类号： G06F3/0658 , G06F3/0626 , G06F3/0689
摘要： There is provided a novel storage system in which the number of signal lines will not increase even if the number of storage devices to be connected in a RAID system increases, and a novel data transfer method to enable a high-speed data transfer even when the transfer rate of the IDE device side is low. A RAID system (10) which is a storage system in which a RAID controller (11) connected to an ATA host and a plurality of IDE devices (12A to 12D, and 22A to 22D) are connected by an IDE bus, characterized in that at least two or more IDE devices are connected to one channel of the IDE bus and said RAID controller and each of said IDE devices are connected by a common data bus and a common address bus within the same channel.
摘要翻译： 提供了一种新颖的存储系统，其中即使要在RAID系统中连接的存储设备的数量增加，信号线的数量也不会增加，并且即使当在RAID系统中连接时也能够进行高速数据传送的新型数据传送方法 IDE设备侧的传输速率较低。 作为存储系统的RAID系统（10），其中连接到ATA主机的RAID控制器（11）和多个IDE设备（12A至12D和22A至22D）通过IDE总线连接，其特征在于， 至少两个或更多个IDE设备连接到IDE总线的一个通道，并且所述RAID控制器和每个所述IDE设备通过公共数据总线和同一通道内的公共地址总线连接。
-
公开(公告)号：US20080301366A1
公开(公告)日：2008-12-04
申请号：US11859411
申请日：2007-09-21
申请人： Hiroto Yoshikawa
发明人： Hiroto Yoshikawa
IPC分类号： G06F12/08
CPC分类号： G06F3/0658 , G06F3/0626 , G06F3/0689
摘要： There is provided a novel storage system in which the number of signal lines will not increase even if the number of storage devices to be connected in a RAID system increases, and a novel data transfer method to enable a high-speed data transfer even when the transfer rate of the IDE device side is low. A RAID system (10) which is a storage system in which a RAID controller (11) connected to an ATA host and a plurality of IDE devices (12A to 12D, and 22A to 22D) are connected by an IDE bus, characterized in that at least two or more IDE devices are connected to one channel of the IDE bus and said RAID controller and each of said IDE devices are connected by a common data bus and a common address bus within the same channel.
摘要翻译： 提供了一种新颖的存储系统，其中即使要在RAID系统中连接的存储设备的数量增加，信号线的数量也不会增加，并且即使当在RAID系统中连接时也能够进行高速数据传送的新型数据传送方法 IDE设备侧的传输速率较低。 作为存储系统的RAID系统（10），其中连接到ATA主机的RAID控制器（11）和多个IDE设备（12A至12D和22A至22D）通过IDE总线连接，其特征在于， 至少两个或更多个IDE设备连接到IDE总线的一个通道，并且所述RAID控制器和每个所述IDE设备通过公共数据总线和同一通道内的公共地址总线连接。
-
公开(公告)号：US20070233907A1
公开(公告)日：2007-10-04
申请号：US11570106
申请日：2005-09-27
IPC分类号： G06F13/38
CPC分类号： G06F13/387 , G06F2213/0038
摘要： A versatile SDIO host controller capable of connecting to standardized general interfaces is provided. An SDIO host controller as a one-chip semiconductor integrated circuit device comprising: at least one core of an SDIO host, the core including an SD host engine and an SD host register set and memory that control the SD host engine; a plurality of CPU interfaces that control the SDIO host; and at least one selector that selects among the CPU interfaces. In particular, the SDIO host controller preferably comprises at least an ATA interface and an ATA-SD protocol conversion engine.
摘要翻译： 提供了能够连接到标准化通用接口的通用SDIO主机控制器。 一种作为单芯片半导体集成电路器件的SDIO主机控制器，包括：SDIO主机的至少一个核心，所述核心包括SD主机引擎和控制SD主机引擎的SD主机寄存器组和存储器; 控制SDIO主机的多个CPU接口; 以及至少一个在CPU接口之间选择的选择器。 特别地，SDIO主机控制器优选地至少包括ATA接口和ATA-SD协议转换引擎。
-
公开(公告)号：US20050028172A1
公开(公告)日：2005-02-03
申请号：US10629842
申请日：2003-07-30
CPC分类号： G06F9/4415
摘要： A method of installing a software program in a host device, which is required for the host device to communicate with a peripheral device. The method includes the steps of coupling the host device to the peripheral device, which contains the software program stored in a memory device contained in the peripheral device, utilizing a USB serial interface; uploading the software program from the peripheral device to the host device; and installing the software program in the host device thereby allowing communication between the host device and the peripheral device.
摘要翻译： 一种在主机设备中安装软件程序的方法，主机设备与外围设备进行通信所需的方法。 该方法包括以下步骤：使用USB串行接口将主机设备耦合到外围设备，该外围设备包含存储在外围设备中的存储设备中的软件程序; 将软件程序从外围设备上传到主机设备; 以及将软件程序安装在主机设备中，从而允许主机设备与外围设备之间的通信。
-
公开(公告)号：US07624216B2
公开(公告)日：2009-11-24
申请号：US11570106
申请日：2005-09-27
IPC分类号： H05K7/10
CPC分类号： G06F13/387 , G06F2213/0038
摘要： A versatile SDIO host controller capable of connecting to standardized general interfaces is provided.An SDIO host controller as a one-chip semiconductor integrated circuit device comprising: at least one core of an SDIO host, the core including an SD host engine and an SD host register set and memory that control the SD host engine; a plurality of CPU interfaces that control the SDIO host; and at least one selector that selects among the CPU interfaces. In particular, the SDIO host controller preferably comprises at least an ATA interface and an ATA-SD protocol conversion engine.
摘要翻译： 提供了能够连接到标准化通用接口的通用SDIO主机控制器。 一种作为单芯片半导体集成电路器件的SDIO主机控制器，包括：SDIO主机的至少一个核心，所述核心包括SD主机引擎和控制SD主机引擎的SD主机寄存器组和存储器; 控制SDIO主机的多个CPU接口; 以及至少一个在CPU接口之间进行选择的选择器。 特别地，SDIO主机控制器优选地至少包括ATA接口和ATA-SD协议转换引擎。
-
-
-
-
-
-
-
搜索结果
8 条记录 (耗时 0.015 秒)
