公开(公告)号：US20060031724A1

公开(公告)日：2006-02-09

申请号：US11246382

申请日：2005-10-07

Applicant: Kazuhisa Ohbuchi ,  Takaharu Nakamura ,  Kazuo Kawabata

Inventor： Kazuhisa Ohbuchi ,  Takaharu Nakamura ,  Kazuo Kawabata

IPC: G06F11/00

CPC classification number: H03M13/2764 ,  H03M13/2703 ,  H03M13/2742

Abstract: An interleaving apparatus comprises a first storing unit for storing data to be transmitted and a first control unit for controlling the first storing unit so that the data to be transmitted is outputted from the first storing unit with the data to be transmitted arranged in a matrix and at least either columns or rows of the data to be transmitted randomly rearranged, facilitating the interleaving. The result is that biased distribution of data, which leads to degradation of the transmission quality, can be prevented relatively easily in a simple structure.

Abstract translation: 交织装置包括：第一存储单元，用于存储要发送的数据;以及第一控制单元，用于控制第一存储单元，使得待发送的数据从第一存储单元输出，要发送的数据以矩阵形式排列; 要传输的数据的至少一列或多行被随机重排，便于交织。 结果是在简单的结构中可以相对容易地防止导致传输质量下降的数据偏置分布。

公开(公告)号：US06971050B1

公开(公告)日：2005-11-29

申请号：US09301853

申请日：1999-04-29

Applicant: Kazuhisa Ohbuchi ,  Takaharu Nakamura ,  Kazuo Kawabata

Inventor： Kazuhisa Ohbuchi ,  Takaharu Nakamura ,  Kazuo Kawabata

IPC: H04L1/00 ,  H03M13/27 ,  G06F11/00

CPC classification number: H03M13/2764 ,  H03M13/2703 ,  H03M13/2742

Abstract: An interleaving apparatus comprises a first storing unit for storing data to be transmitted and a first control unit for controlling the first storing unit so that the data to be transmitted is outputted from the first storing unit with the data to be transmitted arranged in a matrix and at least either columns or rows of the data to be transmitted randomly rearranged, facilitating the interleaving. The result is that biased distribution of data, which leads to degradation of the transmission quality, can be prevented relatively easily in a simple structure.

Abstract translation: 交织装置包括：第一存储单元，用于存储要发送的数据;以及第一控制单元，用于控制第一存储单元，使得待发送的数据从第一存储单元输出，要发送的数据以矩阵形式排列; 要传输的数据的至少一列或多行被随机重排，便于交织。 结果是在简单的结构中可以相对容易地防止导致传输质量下降的数据偏置分布。

公开(公告)号：US07146545B2

公开(公告)日：2006-12-05

申请号：US11246382

申请日：2005-10-07

Applicant: Kazuhisa Ohbuchi ,  Takaharu Nakamura ,  Kazuo Kawabata

Inventor： Kazuhisa Ohbuchi ,  Takaharu Nakamura ,  Kazuo Kawabata

IPC: G06F11/00

CPC classification number: H03M13/2764 ,  H03M13/2703 ,  H03M13/2742

Abstract: An interleaving apparatus comprises a first storing unit for storing data to be transmitted and a first control unit for controlling the first storing unit so that the data to be transmitted is outputted from the first storing unit with the data to be transmitted arranged in a matrix and at least either columns or rows of the data to be transmitted randomly rearranged, facilitating the interleaving. The result is that biased distribution of data, which leads to degradation of the transmission quality, can be prevented relatively easily in a simple structure.

公开(公告)号：US06636549B1

公开(公告)日：2003-10-21

申请号：US09154496

申请日：1998-09-16

Applicant: Takaharu Nakamura ,  Kazuo Kawabata ,  Kazuhisa Ohbuchi

Inventor： Takaharu Nakamura ,  Kazuo Kawabata ,  Kazuhisa Ohbuchi

IPC: H04B169

CPC classification number: H04J13/0074 ,  G06F7/584 ,  G06F7/724 ,  H04B1/69 ,  H04J13/0025 ,  H04L9/0662

Abstract: An n-bit binary value corresponding to an amount of phase shift d is assigned to an SREG, and a shift operation is performed. An n-bit vector value corresponding to a decimal value “1” is assigned to an LAT as an initial value. Thereafter, the input from an SW is sequentially stored. An MUL performs a square operation within a Galois field GF (2n) for the output of the LAT. A DBL performs a double operation within the Galois field GF (2n) for the output of the MUL. The SW selects either of the outputs of the MUL and the DBL according to the output value from the MSB side of the SREG. After the shift operation and the latch operation are performed a number of times n, the n-bit output of the LAT is output as respective phase shift coefficients b0 through bn−1.

Abstract translation: 对应于相移量d的n位二进制值被分配给SREG，并且执行移位操作。 将对应于十进制值“1”的n位向量值分配给LAT作为初始值。 此后，依次存储来自SW的输入。 MUL在Galois域GF（2 ）内执行LAT的输出的平方运算。 DBL在Galois域GF（2 ）中执行双重操作以输出MUL。 SW根据SREG的MSB侧的输出值选择MUL和DBL的任一输出。 在移位操作和锁存操作执行次数n之后，输出LAT的n位输出作为各自的相移系数b0至bn-1。