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    Cell arrangement evaluating method, storage medium storing cell arrangement evaluating program, cell arranging apparatus and method, and storage medium storing cell arranging program
    1.
    发明授权
    Cell arrangement evaluating method, storage medium storing cell arrangement evaluating program, cell arranging apparatus and method, and storage medium storing cell arranging program 失效
    单元布置评估方法，存储介质存储单元布置评估程序，单元布置装置和方法以及存储单元布置程序的存储介质

    公开(公告)号：US06260179B1

    公开(公告)日：2001-07-10

    申请号：US09072357

    申请日：1998-05-05

    申请人： Keiko Ohsawa ,  Terunobu Maruyama

    发明人： Keiko Ohsawa ,  Terunobu Maruyama

    IPC分类号： G06F1750

    CPC分类号： G06F17/5072

    摘要： A cell arrangement evaluating method for predicting a wiring density based on only a cell arranging result prior to initiation of any wiring programs so as to easily perform wiring condition evaluation based on the wiring density within a short time. Two cells to be connected by wiring are selected, and a rectangular region is obtained in which the pins of the two cells to be connected are diagonal verfexes. The probability of wiring between the pins to be connected passing through a certain grid point of wiring grid is calculated. A proportion of the rectangular region occupying each evaluation unit grid is calculated, and then, for each evaluation unit grid, an index for an increase of a wiring density made by the factor of the wiring in the evaluation unit grid is calculated. Then, for each evaluation unit grid, the sum of indexes calculated for all the wiring lines among the cells as a wiring density in the evaluation unit grid is calculated. The cell arrangement evaluation method is used for designing an integrated circuit such an LSI or a circuit on a printed circuit board.

    摘要翻译： 一种用于在开始任何布线程序之前仅基于单元布置结果预测布线密度的单元布置评估方法，以便在短时间内容易地基于布线密度进行布线条件评估。 选择要通过布线连接的两个单元，并且获得矩形区域，其中要连接的两个单元的引脚为对角线。 计算要连接的引脚通过布线网格的某个网格点之间布线的概率。 计算占用每个评估单元网格的矩形区域的一部分，然后，对于每个评估单元网格，计算由评估单元格网格中的布线因子引起的布线密度增加的指标。 然后，对于每个评估单元网格，计算针对作为评估单元网格中的布线密度的单元格中的所有布线计算的索引的总和。 电池布置评估方法用于设计诸如LSI或印刷电路板上的电路的集成电路。

    Method and apparatus for determining locations of circuit elements including sequential circuit elements
    2.
    发明授权
    Method and apparatus for determining locations of circuit elements including sequential circuit elements 失效
    用于确定包括顺序电路元件的电路元件的位置的方法和装置

    公开(公告)号：US06226778B1

    公开(公告)日：2001-05-01

    申请号：US08895233

    申请日：1997-07-16

    申请人： Tadashi Konno ,  Keiko Ohsawa ,  Terunobu Maruyama

    发明人： Tadashi Konno ,  Keiko Ohsawa ,  Terunobu Maruyama

    IPC分类号： G06F1750

    CPC分类号： G06F17/5072

    摘要： A circuit element placement method and apparatus in which circuit elements can surely be placed in a short time even if a circuit scale is increased. For this purpose, there is sequentially executed a first step of determining placement coordinates of sequential logic circuit elements among many circuit elements to be placed and a second step of determining placement coordinates of circuit elements other than the sequential logic circuit elements with consideration given to the placement coordinates of the sequential logic circuit elements, determined in the first step. The method and apparatus are applicable at a time of design of an integrated circuit such as LSI, or a circuit on a printed wiring board.

    摘要翻译： 一种电路元件放置方法和装置，其中电路元件可以在短时间内可靠地放置，即使电路规模增加。 为此，顺序地执行第一步骤，确定要放置的许多电路元件之间的顺序逻辑电路元件的放置坐标;以及第二步骤，其中考虑给定时序逻辑电路元件，确定电路元件之外的电路元件的放置坐标 在第一步确定的顺序逻辑电路元件的放置坐标。 该方法和装置在设计诸如LSI的集成电路或印刷电路板上的电路时是适用的。