公开(公告)号：US07337414B2

公开(公告)日：2008-02-26

申请号：US11398609

申请日：2006-04-06

申请人： Terunobu Maruyama ,  Hiroji Takeyama ,  Takeo Nakamura ,  Mitsuru Satou ,  Yuki Kumon ,  Miki Takagi

发明人： Terunobu Maruyama ,  Hiroji Takeyama ,  Takeo Nakamura ,  Mitsuru Satou ,  Yuki Kumon ,  Miki Takagi

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： The time and trouble of a mismatch cause analysis after logical equivalence verification can be reduced, and design and verification TAT can be shortened. A logical equivalence verifying device performs logical equivalence verification between two circuits, and displays the result of the logical equivalence verification. A preprocessing section 7 performs structural matching so as to determine whether there are portions corresponding in circuit structure to each other in corresponding logic cones of the two circuits. An internal DB 5 records the results of the structural matching as an identifier for each element. A subcone extracting section 8 extracts, as a subcone, a collection of elements, which are mutually to one another and have the same identifier, from each logic cone. A verifying section 9 performs logical equivalence verification between the two circuits for each of the extracted subcones. A display control section 10 displays only those subcones for which the logical equivalence verification has resulted in mismatch.

摘要翻译： 可以减少逻辑等价验证后不匹配原因分析的时间和麻烦，可以缩短设计和验证TAT。 逻辑等价验证装置在两个电路之间执行逻辑等价验证，并显示逻辑等效验证的结果。 预处理部7执行结构匹配，以便确定在两个电路的相应逻辑锥中是否存在与电路结构相对应的部分。 内部DB 5将结构匹配的结果记录为每个元素的标识符。 子提取部分8从每个逻辑锥体中提取彼此相互并且具有相同标识符的元素集合作为子单元。 验证部分9对于每个提取的子晶体执行两个电路之间的逻辑等价性验证。 显示控制部10仅显示逻辑等同性验证导致不匹配的那些子会话。

公开(公告)号：US20060047451A1

公开(公告)日：2006-03-02

申请号：US11022969

申请日：2004-12-28

申请人： Mituru Sato ,  Yuki Kumon ,  Hiroji Takeyama ,  Terunobu Maruyama ,  Miki Takagi ,  Tomoki Kanemochi

发明人： Mituru Sato ,  Yuki Kumon ,  Hiroji Takeyama ,  Terunobu Maruyama ,  Miki Takagi ,  Tomoki Kanemochi

IPC分类号： G01R13/00

CPC分类号： G06F17/5045

摘要： A circuit diagram display apparatus displays a plurality of logic circuit diagrams. An associating unit associates the logic circuits based on at least any one of identification information, structural information, logical equivalence information, and external designated information about the logic circuits. A display format changing unit changes a display format between a side-by-side format and one-below-the-other format. A display controller performs control to display a target point in the logic circuit diagram in the same position before and after the display format is changed.

摘要翻译： 电路图显示装置显示多个逻辑电路图。 关联单元基于识别信息，结构信息，逻辑等价信息和关于逻辑电路的外部指定信息中的至少一个来关联逻辑电路。 显示格式改变单元改变并排格式和一种在另一种格式之间的显示格式。 显示控制器执行控制以在显示格式改变之前和之后在相同位置显示逻辑电路图中的目标点。

公开(公告)号：US06240541B1

公开(公告)日：2001-05-29

申请号：US09227967

申请日：1999-01-11

申请人： Mitsuru Yasuda ,  Hiroyuki Sugiyama ,  Noriyuki Ito ,  Ryoichi Yamashita ,  Tadashi Konno ,  Yasunori Abe ,  Naomi Bizen ,  Terunobu Maruyama ,  Yoshiyuki Kato ,  Tomoyuki Isomura ,  Hiroshi Ikeda ,  Miki Takagi

发明人： Mitsuru Yasuda ,  Hiroyuki Sugiyama ,  Noriyuki Ito ,  Ryoichi Yamashita ,  Tadashi Konno ,  Yasunori Abe ,  Naomi Bizen ,  Terunobu Maruyama ,  Yoshiyuki Kato ,  Tomoyuki Isomura ,  Hiroshi Ikeda ,  Miki Takagi

IPC分类号： G06F1750

CPC分类号： G06F17/5022

摘要： A circuit designing apparatus of an interactive type which enables a simplified and highspeed circuit design process while largely reducing a burden on a designer, having a speed analyzing unit for conducting a delay computation for each wiring path on a circuit to be designed and a display control unit for displaying a result of the delay computation by the speed analyzing unit on a display unit. When the speed analyzing unit conducts a delay computation, a delay value of each logic component forming the circuit that is an object of the design is set and altered according to a dullness of a signal waveform inputted to the logic component. The circuit designing apparatus of an interactive type may be applied to a system for conducting a circuit design of an integrated circuit such as an LSI or the like or a printed circuit board.

摘要翻译： 一种交互式的电路设计装置，其能够实现简化和高速电路设计过程，同时大大减轻设计者的负担，具有用于对要设计的电路上的每个布线路径进行延迟计算的速度分析单元和显示控制 单元，用于在显示单元上显示速度分析单元的延迟计算结果。 当速度分析单元进行延迟计算时，根据输入到逻辑部件的信号波形的钝度来设定和改变形成作为设计对象的电路的每个逻辑部件的延迟值。 交互式的电路设计装置可以应用于用于进行诸如LSI等的集成电路的电路设计的系统或印刷电路板。

公开(公告)号：US5787268A

公开(公告)日：1998-07-28

申请号：US497375

申请日：1995-06-30

申请人： Yaroku Sugiyama ,  Hiroyuki Sugiyama ,  Noriyuki Ito ,  Ryouichi Yamashita ,  Terunobu Maruyama ,  Yasunori Abe

发明人： Yaroku Sugiyama ,  Hiroyuki Sugiyama ,  Noriyuki Ito ,  Ryouichi Yamashita ,  Terunobu Maruyama ,  Yasunori Abe

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5022 ,  G06F17/5045

摘要： The invention provides an interactive circuit designing apparatus wherein a logic design, a layout design and a speed analysis can cooperate with each other in processing. The interactive circuit designing apparatus comprises a logical designing section for logically designing a design object circuit, a layout designing section for performing mounting arrangement of logical components constituting a design object circuit based on a result of the logical design and performing wiring between the logical components, and a speed analysis section for performing a speed analysis based on calculation of a delay for each of paths on the design object circuit in accordance with a result of the layout. The logical designing section, the layout designing section and the speed analysis section are connected to each other so as to cooperate with each other when necessary. The interactive circuit designing apparatus is applied to an apparatus for designing a circuit of an LSI, a printed circuit board or a like element.

摘要翻译： 本发明提供了一种交互式电路设计装置，其中逻辑设计，布局设计和速度分析可以在处理中相互配合。 交互式电路设计装置包括用于逻辑设计设计对象电路的逻辑设计部分，布局设计部分，用于基于逻辑设计的结果执行构成设计对象电路的逻辑部件的安装布置，并且在逻辑部件之间执行布线， 以及速度分析部件，用于根据布局的结果，基于对设计对象电路中的每个路径的延迟的计算来执行速度分析。 逻辑设计部分，布局设计部分和速度分析部分彼此连接，以便在必要时相互配合。 交互式电路设计装置适用于设计LSI，印刷电路板等元件的电路的装置。

公开(公告)号：US06260179B1

公开(公告)日：2001-07-10

申请号：US09072357

申请日：1998-05-05

申请人： Keiko Ohsawa ,  Terunobu Maruyama

发明人： Keiko Ohsawa ,  Terunobu Maruyama

IPC分类号： G06F1750

CPC分类号： G06F17/5072

摘要： A cell arrangement evaluating method for predicting a wiring density based on only a cell arranging result prior to initiation of any wiring programs so as to easily perform wiring condition evaluation based on the wiring density within a short time. Two cells to be connected by wiring are selected, and a rectangular region is obtained in which the pins of the two cells to be connected are diagonal verfexes. The probability of wiring between the pins to be connected passing through a certain grid point of wiring grid is calculated. A proportion of the rectangular region occupying each evaluation unit grid is calculated, and then, for each evaluation unit grid, an index for an increase of a wiring density made by the factor of the wiring in the evaluation unit grid is calculated. Then, for each evaluation unit grid, the sum of indexes calculated for all the wiring lines among the cells as a wiring density in the evaluation unit grid is calculated. The cell arrangement evaluation method is used for designing an integrated circuit such an LSI or a circuit on a printed circuit board.

摘要翻译： 一种用于在开始任何布线程序之前仅基于单元布置结果预测布线密度的单元布置评估方法，以便在短时间内容易地基于布线密度进行布线条件评估。 选择要通过布线连接的两个单元，并且获得矩形区域，其中要连接的两个单元的引脚为对角线。 计算要连接的引脚通过布线网格的某个网格点之间布线的概率。 计算占用每个评估单元网格的矩形区域的一部分，然后，对于每个评估单元网格，计算由评估单元格网格中的布线因子引起的布线密度增加的指标。 然后，对于每个评估单元网格，计算针对作为评估单元网格中的布线密度的单元格中的所有布线计算的索引的总和。 电池布置评估方法用于设计诸如LSI或印刷电路板上的电路的集成电路。

公开(公告)号：US06226778B1

公开(公告)日：2001-05-01

申请号：US08895233

申请日：1997-07-16

申请人： Tadashi Konno ,  Keiko Ohsawa ,  Terunobu Maruyama

发明人： Tadashi Konno ,  Keiko Ohsawa ,  Terunobu Maruyama

IPC分类号： G06F1750

CPC分类号： G06F17/5072

摘要： A circuit element placement method and apparatus in which circuit elements can surely be placed in a short time even if a circuit scale is increased. For this purpose, there is sequentially executed a first step of determining placement coordinates of sequential logic circuit elements among many circuit elements to be placed and a second step of determining placement coordinates of circuit elements other than the sequential logic circuit elements with consideration given to the placement coordinates of the sequential logic circuit elements, determined in the first step. The method and apparatus are applicable at a time of design of an integrated circuit such as LSI, or a circuit on a printed wiring board.

摘要翻译： 一种电路元件放置方法和装置，其中电路元件可以在短时间内可靠地放置，即使电路规模增加。 为此，顺序地执行第一步骤，确定要放置的许多电路元件之间的顺序逻辑电路元件的放置坐标;以及第二步骤，其中考虑给定时序逻辑电路元件，确定电路元件之外的电路元件的放置坐标 在第一步确定的顺序逻辑电路元件的放置坐标。 该方法和装置在设计诸如LSI的集成电路或印刷电路板上的电路时是适用的。

公开(公告)号：US5892685A

公开(公告)日：1999-04-06

申请号：US669766

申请日：1996-06-25

申请人： Hiroyuki Sugiyama ,  Terunobu Maruyama ,  Ryouichi Yamashita

发明人： Hiroyuki Sugiyama ,  Terunobu Maruyama ,  Ryouichi Yamashita

IPC分类号： G06F17/50 ,  G06F17/00

CPC分类号： G06F17/5068

摘要： A packaging design system for an LSI circuit includes: a gate placement preparation unit for preparing basic placement data for gates used as an original data for producting the LSI circuit; a wiring data preparation unit operatively connected to the gate placement preparation unit for preparing wiring data based on wiring patterns each having the same length between gates; a delay calculation unit operatively connected to the wiring data preparation unit for calculating net delays between gates and path delays from a clock input until an output in the LSI circuit; a standard path delay determining unit operatively connected to the delay calculation unit for determining a standard path delay in accordance with distribution of path delays; and a macro determining unit operatively connected to the standard path delay determining unit for selecting the macros in accordance with predetermined conditions of path delays, and selected several macros being used for an actual placement of gates.

摘要翻译： LSI电路的封装设计系统包括：栅极布置准备单元，用于准备用作用于产生LSI电路的原始数据的门的基本布局数据; 布线数据准备单元，其可操作地连接到所述栅极布置准备单元，用于基于栅极之间具有相同长度的布线图形来准备布线数据; 延迟计算单元，可操作地连接到所述布线数据准备单元，用于计算从时钟输入到LSI电路的输出之间的门与路径延迟之间的净延迟; 标准路径延迟确定单元，可操作地连接到所述延迟计算单元，用于根据路径延迟的分布确定标准路径延迟; 以及宏确定单元，其可操作地连接到标准路径延迟确定单元，用于根据路径延迟的预定条件选择宏，以及选择的几个宏用于门的实际放置。

公开(公告)号：US20060184903A1

公开(公告)日：2006-08-17

申请号：US11398609

申请日：2006-04-06

申请人： Terunobu Maruyama ,  Hiroji Takeyama ,  Takeo Nakamura ,  Mitsuru Satou ,  Yuki Kumon ,  Miki Takagi

发明人： Terunobu Maruyama ,  Hiroji Takeyama ,  Takeo Nakamura ,  Mitsuru Satou ,  Yuki Kumon ,  Miki Takagi

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： The time and trouble of a mismatch cause analysis after logical equivalence verification can be reduced, and design and verification TAT can be shortened. A logical equivalence verifying device performs logical equivalence verification between two circuits, and displays the result of the logical equivalence verification. A preprocessing section 7 performs structural matching so as to determine whether there are portions corresponding in circuit structure to each other in corresponding logic cones of the two circuits. An internal DB 5 records the results of the structural matching as an identifier for each element. A subcone extracting section 8 extracts, as a subcone, a collection of elements, which are mutually to one another and have the same identifier, from each logic cone. A verifying section 9 performs logical equivalence verification between the two circuits for each of the extracted subcones. A display control section 10 displays only those subcones for which the logical equivalence verification has resulted in mismatch.

摘要翻译： 可以减少逻辑等价验证后不匹配原因分析的时间和麻烦，可以缩短设计和验证TAT。 逻辑等价验证装置在两个电路之间执行逻辑等价验证，并显示逻辑等效验证的结果。 预处理部7执行结构匹配，以便确定在两个电路的相应逻辑锥中是否存在与电路结构相对应的部分。 内部DB 5将结构匹配的结果记录为每个元素的标识符。 子提取部分8从每个逻辑锥体中提取彼此相互并且具有相同标识符的元素集合作为子单元。 验证部分9对于每个提取的子晶体执行两个电路之间的逻辑等价性验证。 显示控制部10仅显示逻辑等同性验证导致不匹配的那些子会话。

公开(公告)号：US5889677A

公开(公告)日：1999-03-30

申请号：US574901

申请日：1995-12-19

申请人： Mitsuru Yasuda ,  Hiroyuki Sugiyama ,  Noriyuki Ito ,  Ryoichi Yamashita ,  Tadashi Konno ,  Yasunori Abe ,  Naomi Bizen ,  Terunobu Maruyama ,  Yoshiyuki Kato ,  Tomoyuki Isomura ,  Hiroshi Ikeda ,  Miki Takagi

发明人： Mitsuru Yasuda ,  Hiroyuki Sugiyama ,  Noriyuki Ito ,  Ryoichi Yamashita ,  Tadashi Konno ,  Yasunori Abe ,  Naomi Bizen ,  Terunobu Maruyama ,  Yoshiyuki Kato ,  Tomoyuki Isomura ,  Hiroshi Ikeda ,  Miki Takagi

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A circuit designing apparatus of an interactive type which enables a simplified and high-speed circuit design process while largely reducing a burden on a designer, having a speed analyzing unit for conducting a delay computation for each wiring path on a circuit to be designed and a display control unit for displaying a result of the delay computation by the speed analyzing unit on a display unit. When the speed analyzing unit conducts a delay computation, a delay value of each logic component forming the circuit that is an object of the design is set and altered according to a dullness of a signal waveform inputted to the logic component. The circuit designing apparatus of an interactive type may be applied to a system for conducting a circuit design of an integrated circuit such as an LSI or the like or a printed circuit board.

摘要翻译： 一种交互式的电路设计装置，其能够实现简化和高速电路设计过程，同时大大减轻设计者的负担，具有速度分析单元，用于对要设计的电路上的每个布线路径执行延迟计算，以及 显示控制单元，用于在显示单元上显示速度分析单元的延迟计算结果。 当速度分析单元进行延迟计算时，根据输入到逻辑部件的信号波形的钝度来设定和改变形成作为设计对象的电路的每个逻辑部件的延迟值。 交互式的电路设计装置可以应用于用于进行诸如LSI等的集成电路的电路设计的系统或印刷电路板。

公开(公告)号：US07143375B2

公开(公告)日：2006-11-28

申请号：US10705787

申请日：2003-11-12

申请人： Terunobu Maruyama ,  Hiroji Takeyama ,  Takeo Nakamura ,  Mitsuru Satou ,  Yuki Kumon ,  Miki Takagi

发明人： Terunobu Maruyama ,  Hiroji Takeyama ,  Takeo Nakamura ,  Mitsuru Satou ,  Yuki Kumon ,  Miki Takagi

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： The time and trouble of a mismatch cause analysis after logical equivalence verification can be reduced, and design and verification TAT can be shortened. A logical equivalence verifying device performs logical equivalence verification between two circuits, and displays the result of the logical equivalence verification. A preprocessing section 7 performs structural matching so as to determine whether there are portions corresponding in circuit structure to each other in corresponding logic cones of the two circuits. An internal DB 5 records the results of the structural matching as an identifier for each element. A subcone extracting section 8 extracts, as a subcone, a collection of elements, which are mutually to one another and have the same identifier, from each logic cone. A verifying section 9 performs logical equivalence verification between the two circuits for each of the extracted subcones. A display control section 10 displays only those subcones for which the logical equivalence verification has resulted in mismatch.

摘要翻译： 可以减少逻辑等价验证后不匹配原因分析的时间和麻烦，可以缩短设计和验证TAT。 逻辑等价验证装置在两个电路之间执行逻辑等价验证，并显示逻辑等效验证的结果。 预处理部7执行结构匹配，以便确定在两个电路的相应逻辑锥中是否存在与电路结构相对应的部分。 内部DB 5将结构匹配的结果记录为每个元素的标识符。 子提取部分8从每个逻辑锥体中提取彼此相互并且具有相同标识符的元素集合作为子单元。 验证部分9对于每个提取的子晶体执行两个电路之间的逻辑等价性验证。 显示控制部10仅显示逻辑等同性验证导致不匹配的那些子会话。