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    N/P CONFIGURABLE LDMOS SUBCIRCUIT MACRO MODEL
    1.
    发明申请
    N/P CONFIGURABLE LDMOS SUBCIRCUIT MACRO MODEL 有权
    N / P可配置LDMOS SUBCIRCUIT MACRO MODEL

    公开(公告)号：US20120102443A1

    公开(公告)日：2012-04-26

    申请号：US13277932

    申请日：2011-10-20

    申请人： Yong LIU ,  Keith R. GREEN ,  Marie DENISON ,  Yizhong XIE

    发明人： Yong LIU ,  Keith R. GREEN ,  Marie DENISON ,  Yizhong XIE

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5022 ,  G06F17/5054

    摘要： A process of operating a computer system to create a subcircuit model of an N/P configurable extended drain MOS transistor in which the subcircuit model includes an npn bipolar transistor and a pnp bipolar transistor which correspond to current paths through n-channel drift lanes and p-channel drift lanes during dual mode operation. A process of operating a computer system to simulate the behavior of an electronic circuit including a N/P configurable extended drain MOS transistor in which a subcircuit model of the N/P configurable extended drain MOS transistor includes an npn bipolar transistor and a pnp bipolar transistor which correspond to current paths through n-channel drift lanes and p-channel drift lanes during dual mode operation. A computer readable medium storing an electronic circuit simulation program that generates a simulation output of the behavior of an electronic circuit including a N/P configurable extended drain MOS transistor.

    摘要翻译： 一种操作计算机系统以创建N / P可配置扩展漏极MOS晶体管的分支电路模型的过程，其中子电路模型包括npn双极晶体管和pnp双极晶体管，其对应于通过n沟道漂移通道的电流路径和p - 双通道行车道。 一种操作计算机系统以模拟包括N / P可配置扩展漏极MOS晶体管的电子电路的行为的过程，其中N / P可配置扩展漏极MOS晶体管的子电路模型包括npn双极晶体管和pnp双极晶体管 其对应于在双模式操作期间通过n沟道漂移通道和p沟道漂移通道的电流路径。 一种存储电子电路仿真程序的计算机可读介质，其生成包括N / P可配置扩展漏极MOS晶体管的电子电路的行为的模拟输出。

    Modeling of Ferroelectric Capacitors to Include Local Statistical Variations of Ferroelectric Properties
    2.
    发明申请
    Modeling of Ferroelectric Capacitors to Include Local Statistical Variations of Ferroelectric Properties 有权
    铁电电容的建模包括铁电性质的局部统计变化

    公开(公告)号：US20100299115A1

    公开(公告)日：2010-11-25

    申请号：US12568910

    申请日：2009-09-29

    申请人： Borna Obradovic ,  Keith R. Green ,  Scott R. Summerfelt

    发明人： Borna Obradovic ,  Keith R. Green ,  Scott R. Summerfelt

    IPC分类号： G06F17/10

    CPC分类号： G06F17/5036

    摘要： Simulation of an electronic circuit including a model of a ferroelectric capacitor. The model of the ferroelectric capacitor includes a multi-domain ferroelectric capacitor, in which each of the domains is associated with a positive and a negative coercive voltage. A probability distribution function of positive and negative coercive voltages is defined, from which a weighting function of the distribution of domains having those coercive voltages is defined. To create a model of a small ferroelectric capacitor, a Poisson probability distribution is assigned to each of an array of gridcells defining the probability distribution function of positive and negative coercive voltages, and a number of domains assigned to each gridcell is randomly selected according to that Poisson distribution and an expected number of domains in the modeled capacitor for that gridcell, based on the area of the modeled capacitor. The electrical behavior of the ferroelectric capacitor is evaluated by evaluating the superposed polarization of each of the randomly selected domains.

    摘要翻译： 包括铁电电容器型号的电子电路仿真。 铁电电容器的模型包括多畴铁电电容器，其中每个畴与正矫顽电压和负矫顽电压相关联。 定义正矫顽电压和负矫顽电压的概率分布函数，从而确定具有矫顽电压的域的分布的加权函数。 为了创建小型铁电电容器的模型，将Poisson概率分布分配给定义正和负矫顽电压的概率分布函数的网格单元阵列中的每一个，并且分配给每个网格单元的域的数量根据该格子随机选择 基于建模电容器的面积，该网格单元的建模电容器的泊松分布和预期数量的域。 通过评估每个随机选择的畴的叠加极化来评估铁电电容器的电性能。

    METHOD AND SYSTEM FOR MODELING AN LDMOS TRANSISTOR
    3.
    发明申请
    METHOD AND SYSTEM FOR MODELING AN LDMOS TRANSISTOR 审中-公开
    用于建模LDMOS晶体管的方法和系统

    公开(公告)号：US20100241413A1

    公开(公告)日：2010-09-23

    申请号：US12406423

    申请日：2009-03-18

    申请人： Yong Liu ,  Keith R. Green ,  Sameer Pendharkar

    发明人： Yong Liu ,  Keith R. Green ,  Sameer Pendharkar

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： A processor with a computer program product embodied thereon for modeling an LDMOS transistor having a drift region is provided. Characteristic behavior of a CMOS transistor with its body coupled to its source is generated, and characteristic behavior of a resistor is generated, where the resistor is coupled to the drain of the CMOS transistor. Then to account for impact ionization, an impact ionization current for electrons in the drift region an impact ionization current for holes in the drift region are calculated.

    摘要翻译： 提供了一种其上实施有用于对具有漂移区域的LDMOS晶体管进行建模的计算机程序产品的处理器。 产生其主体与其源极耦合的CMOS晶体管的特性，并且产生电阻器的特性，其中电阻器耦合到CMOS晶体管的漏极。 然后考虑到冲击电离，计算漂移区域中电子的冲击电离电流对漂移区中空穴的电离电流。

    Vacuum cleaner height adjustment
    4.
    发明授权
    Vacuum cleaner height adjustment 有权
    吸尘器高度调节

    公开(公告)号：US07353563B2

    公开(公告)日：2008-04-08

    申请号：US10888287

    申请日：2004-07-09

    申请人： Douglas L. Blocker ,  Keith R. Green ,  Richard J. Reis

    发明人： Douglas L. Blocker ,  Keith R. Green ,  Richard J. Reis

    IPC分类号： A47L5/34

    CPC分类号： A47L5/34

    摘要： A vacuum cleaner height adjustment mechanism including a cleaning head having a pair of laterally spaced front wheels and a pair of laterally spaced rear wheels mounted for rotation within the cleaning head for supporting the cleaning head on a floor during vacuum cleaning operations, the front wheels being mounted to a common axle mounted in the cleaning head for pivotal movement around a fixed axis, the wheels being mounted to the axle offset from the pivotal axis of the axle, an arm extending from the axle, a shaft mounted substantially horizontally in the cleaning head for rotation about a central axis disposed in a plane perpendicular to a plane containing the axis of the axle, one end of the shaft having spiral threads thereon and an opposite end having an adjustment knob fixed thereto for manually rotating the shaft, and a guide member having internal threads matching and engaged with the spiral threads on the shaft for movement along the shaft, the guide member being coupled to the arm extending from the axle so as to pivot the axle when the shaft is rotated by rotating the knob, whereby the front wheels are raised or lowered relative to the cleaning head.

    摘要翻译： 一种真空吸尘器高度调节机构，包括具有一对横向间隔开的前轮的清洁头和一对安装成在清洁头内旋转的横向间隔开的后轮，用于在真空清洁操作期间将清洁头支撑在地板上，前轮是 安装在安装在清洁头中的公共轴上用于围绕固定轴线枢转运动，所述车轮安装到从轴的枢转轴线偏移的轴上，从车轴延伸的臂，大致水平地安装在清洁头中的轴 为了围绕设置在垂直于包含轴的轴线的平面的平面中的中心轴旋转，所述轴的一端具有螺旋线，并且具有固定到其上的用于手动旋转轴的调节旋钮的相对端，以及引导构件 其具有与所述轴上的所述螺旋螺纹相配合并与所述轴一起运动的内螺纹，所述引导构件联接到所述螺纹 所述臂从所述轴延伸，以便当所述轴通过旋转所述旋钮而旋转时枢轴，由此所述前轮相对于所述清洁头升高或降低。

    Hall effect device having voltage based biasing for temperature compensation
    6.
    发明授权
    Hall effect device having voltage based biasing for temperature compensation 有权
    具有用于温度补偿的基于电压的偏置的霍尔效应器件

    公开(公告)号：US09013167B2

    公开(公告)日：2015-04-21

    申请号：US12942529

    申请日：2010-11-09

    申请人： Anthony G. Antonacci ,  Keith R. Green ,  Borna J. Obradovic

    发明人： Anthony G. Antonacci ,  Keith R. Green ,  Borna J. Obradovic

    IPC分类号： G01R19/32 ,  G01R33/07 ,  G01R33/00

    CPC分类号： G01R33/072 ,  G01R33/0029

    摘要： A Hall effect device includes a Hall element and a voltage regulator. The Hall element has first and second bias terminals, or nodes. The Hall effect device maintains, or regulates, a voltage at a point within the Hall element between the first and second bias terminals at about a constant voltage level, while generating a Hall effect voltage. In particular embodiments, the Hall effect voltage is, thus, prevented from substantially varying with the temperature of the Hall element.

    摘要翻译： 霍尔效应装置包括霍尔元件和电压调节器。 霍尔元件具有第一和第二偏置端子或节点。 在产生霍尔效应电压的同时，霍尔效应器件在大约恒定的电压电平下维持或调节第一和第二偏置端子之间的霍尔元件内的点处的电压。 在具体实施例中，因此霍尔效应电压被防止与霍尔元件的温度基本上变化。

    Modeling of ferroelectric capacitors to include local statistical variations of ferroelectric properties
    7.
    发明授权
    Modeling of ferroelectric capacitors to include local statistical variations of ferroelectric properties 有权
    铁电电容器的建模包括铁电性质的局部统计变化

    公开(公告)号：US08380476B2

    公开(公告)日：2013-02-19

    申请号：US12568910

    申请日：2009-09-29

    申请人： Borna Obradovic ,  Keith R. Green ,  Scott R. Summerfelt

    发明人： Borna Obradovic ,  Keith R. Green ,  Scott R. Summerfelt

    IPC分类号： G06F17/50 ,  G06G7/62

    CPC分类号： G06F17/5036

    摘要： Simulation of an electronic circuit including a model of a ferroelectric capacitor. The model of the ferroelectric capacitor includes a multi-domain ferroelectric capacitor, in which each of the domains is associated with a positive and a negative coercive voltage. A probability distribution function of positive and negative coercive voltages is defined, from which a weighting function of the distribution of domains having those coercive voltages is defined. To create a model of a small ferroelectric capacitor, a Poisson probability distribution is assigned to each of an array of gridcells defining the probability distribution function of positive and negative coercive voltages, and a number of domains assigned to each gridcell is randomly selected according to that Poisson distribution and an expected number of domains in the modeled capacitor for that gridcell, based on the area of the modeled capacitor. The electrical behavior of the ferroelectric capacitor is evaluated by evaluating the superposed polarization of each of the randomly selected domains.

    摘要翻译： 包括铁电电容器型号的电子电路仿真。 铁电电容器的模型包括多畴铁电电容器，其中每个畴与正矫顽电压和负矫顽电压相关联。 定义正矫顽电压和负矫顽电压的概率分布函数，从而确定具有矫顽电压的域的分布的加权函数。 为了创建小型铁电电容器的模型，将Poisson概率分布分配给定义正和负矫顽电压的概率分布函数的网格单元阵列中的每一个，并且分配给每个网格单元的域的数量根据该格子随机选择 基于建模电容器的面积，该网格单元的建模电容器的泊松分布和预期数量的域。 通过评估每个随机选择的畴的叠加极化来评估铁电电容器的电性能。

    N/P configurable LDMOS subcircuit macro model
    9.
    发明授权
    N/P configurable LDMOS subcircuit macro model 有权
    N / P可配置LDMOS子电路宏模型

    公开(公告)号：US08429592B2

    公开(公告)日：2013-04-23

    申请号：US13277932

    申请日：2011-10-20

    申请人： Yong Liu ,  Keith R. Green ,  Marie Denison ,  Yizhong Xie

    发明人： Yong Liu ,  Keith R. Green ,  Marie Denison ,  Yizhong Xie

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5022 ,  G06F17/5054

    摘要： A process of operating a computer system to create a subcircuit model of an N/P configurable extended drain MOS transistor in which the subcircuit model includes an npn bipolar transistor and a pnp bipolar transistor which correspond to current paths through n-channel drift lanes and p-channel drift lanes during dual mode operation. A process of operating a computer system to simulate the behavior of an electronic circuit including a N/P configurable extended drain MOS transistor in which a subcircuit model of the N/P configurable extended drain MOS transistor includes an npn bipolar transistor and a pnp bipolar transistor which correspond to current paths through n-channel drift lanes and p-channel drift lanes during dual mode operation. A computer readable medium storing an electronic circuit simulation program that generates a simulation output of the behavior of an electronic circuit including a N/P configurable extended drain MOS transistor.

    摘要翻译： 一种操作计算机系统以创建N / P可配置扩展漏极MOS晶体管的分支电路模型的过程，其中子电路模型包括npn双极晶体管和pnp双极晶体管，其对应于通过n沟道漂移通道的电流路径和p - 双通道行车道。 一种操作计算机系统以模拟包括N / P可配置扩展漏极MOS晶体管的电子电路的行为的过程，其中N / P可配置扩展漏极MOS晶体管的子电路模型包括npn双极晶体管和pnp双极晶体管 其对应于在双模式操作期间通过n沟道漂移通道和p沟道漂移通道的电流路径。 一种存储电子电路仿真程序的计算机可读介质，其生成包括N / P可配置扩展漏极MOS晶体管的电子电路的行为的模拟输出。

    Hall Effect Device
    10.
    发明申请
    Hall Effect Device 有权
    霍尔效应器

    公开(公告)号：US20120112733A1

    公开(公告)日：2012-05-10

    申请号：US12942529

    申请日：2010-11-09

    申请人： Anthony G. Antonacci ,  Keith R. Green ,  Borna J. Obradovic

    发明人： Anthony G. Antonacci ,  Keith R. Green ,  Borna J. Obradovic

    IPC分类号： H03H1/00

    CPC分类号： G01R33/072 ,  G01R33/0029

    摘要： A Hall effect device includes a Hall element and a voltage regulator. The Hall element has first and second bias terminals, or nodes. The Hall effect device maintains, or regulates, a voltage at a point within the Hall element between the first and second bias terminals at about a constant voltage level, while generating a Hall effect voltage. In particular embodiments, the Hall effect voltage is, thus, prevented from substantially varying with the temperature of the Hall element.

    摘要翻译： 霍尔效应装置包括霍尔元件和电压调节器。 霍尔元件具有第一和第二偏置端子或节点。 在产生霍尔效应电压的同时，霍尔效应器件在大约恒定的电压电平下维持或调节第一和第二偏置端子之间的霍尔元件内的点处的电压。 在具体实施例中，因此霍尔效应电压被防止与霍尔元件的温度基本上变化。