公开(公告)号：US08291291B1

公开(公告)日：2012-10-16

申请号：US12291695

申请日：2008-11-13

申请人： Zhengjun Pan ,  Suleyman Sirri Demirsoy ,  Volker Mauer ,  Kellie Marks

发明人： Zhengjun Pan ,  Suleyman Sirri Demirsoy ,  Volker Mauer ,  Kellie Marks

IPC分类号： G06F11/00

CPC分类号： H03M13/2739 ,  H03M13/2764 ,  H03M13/2775 ,  H03M13/6525 ,  H03M13/6561 ,  H04L1/0071

摘要： Interleaving in which functions relating final and original positions are implemented with low complexity using inequalities based on the functions.

摘要翻译： 使用基于功能的不等式，以最低复杂度实现关于最终和原始职位的功能的交织。

公开(公告)号：US08629691B2

公开(公告)日：2014-01-14

申请号：US13474070

申请日：2012-05-17

申请人： Michael Fitton ,  Kulwinder Dhanoa ,  Benjamin Thomas Cope ,  Kellie Marks ,  Lei Xu

发明人： Michael Fitton ,  Kulwinder Dhanoa ,  Benjamin Thomas Cope ,  Kellie Marks ,  Lei Xu

IPC分类号： H03K19/177 ,  G06F1/26

CPC分类号： H03K19/017581 ,  G06F13/385

摘要： Systems and methods are disclosed for interfacing between hard logic elements and soft logic elements implemented on an integrated device. In particular, a configurable interface is provided that includes interconnects between hard logic and soft logic, which enable signals to be selectively routed between the inputs and outputs of hard logic blocks and soft logic modules. The interconnects allow for certain hard logic blocks to be bypassed in favor of soft logic functionality. Moreover, the interconnects allow soft logic to augment the processing of hard logic blocks, e.g., by providing additional signals to the hard logic block.

摘要翻译： 公开了用于在集成设备上实现的硬逻辑元件和软逻辑元件之间的接口的系统和方法。 特别地，提供了包括硬逻辑和软逻辑之间的互连的可配置接口，其使信号能够在硬逻辑块和软逻辑模块的输入和输出之间选择性地路由。 互连允许绕过某些硬逻辑块以有利于软逻辑功能。 此外，互连允许软逻辑来增加硬逻辑块的处理，例如通过向硬逻辑块提供附加信号。

公开(公告)号：US08060729B1

公开(公告)日：2011-11-15

申请号：US12244904

申请日：2008-10-03

申请人： Steven Perry ,  Martin Roberts ,  Kellie Marks

发明人： Steven Perry ,  Martin Roberts ,  Kellie Marks

IPC分类号： G06F9/00

CPC分类号： G06F15/7892

摘要： In the provided architecture, one or more multi-threaded processors may be combined with hardware blocks having increased functionality. Each hardware block may be able to transfer a data packet to a particular hardware block based on the packet being processing. One or more hardware block may also be able to divide packets into subpackets for separate processing, and other hardware blocks may be able to rejoin the subpackets. Hardware blocks may also be able to transfer packet information between other hardware blocks during the processing sequence.

摘要翻译： 在所提供的架构中，一个或多个多线程处理器可以与具有增加的功能的硬件块组合。 每个硬件块可能能够基于正在处理的分组将数据分组传送到特定的硬件块。 一个或多个硬件块还可能能够将分组划分为子分组以进行单独处理，并且其他硬件块可能能够重新加入子分组。 硬件块也可以在处理序列期间在其它硬件块之间传送分组信息。

公开(公告)号：US08812819B1

公开(公告)日：2014-08-19

申请号：US13212377

申请日：2011-08-18

申请人： Martin Langhammer ,  Kellie Marks

发明人： Martin Langhammer ,  Kellie Marks

IPC分类号： G06F12/00

CPC分类号： G06F17/142

摘要： Data signal items output by a radix 4n2m fast Fourier transform (“FFT”) operation may not be in the order desired for further use of those data items (e.g., they may be output in a non-natural order rather than in a desired natural order). Memory circuitry (e.g., dual-port memory circuitry) may be used in conjunction with circuitry for addressing the memory circuitry with address signals that are reordered in a particular way for each successive set of N data items. This allows use of memory circuitry with fewer data item storage locations than would otherwise be required to reorder the data items from non-natural to natural order. In particular, the memory circuitry only needs to be able to store N data items at any one time, which is more efficient memory utilization than would otherwise be possible.

摘要翻译： 通过基数4n2m快速傅立叶变换（“FFT”）操作输出的数据信号项可能不符合进一步使用这些数据项所需的顺序（例如，它们可以以非自然的顺序而不是以期望的自然顺序输出 订购）。 存储器电路（例如，双端口存储器电路）可以与电路一起使用，该电路用于以对于每个连续的N个数据项集合的特定方式重新排序的地址信号来寻址存储器电路。 这允许使用存储器电路与数据项存储位置相比，否则将重新排序数据项从非自然顺序到自然顺序。 特别地，存储器电路仅需要能够在任何一个时间存储N个数据项，这比其他情况下更有效的存储器利用。

公开(公告)号：US20120319730A1

公开(公告)日：2012-12-20

申请号：US13474070

申请日：2012-05-17

申请人： Michael Fitton ,  Kulwinder Dhanoa ,  Benjamin Thomas Cope ,  Kellie Marks ,  Lei Xu

发明人： Michael Fitton ,  Kulwinder Dhanoa ,  Benjamin Thomas Cope ,  Kellie Marks ,  Lei Xu

IPC分类号： H03K19/177

CPC分类号： H03K19/017581 ,  G06F13/385

摘要： Systems and methods are disclosed for interfacing between hard logic elements and soft logic elements implemented on an integrated device. In particular, a configurable interface is provided that includes interconnects between hard logic and soft logic, which enable signals to be selectively routed between the inputs and outputs of hard logic blocks and soft logic modules. The interconnects allow for certain hard logic blocks to be bypassed in favor of soft logic functionality. Moreover, the interconnects allow soft logic to augment the processing of hard logic blocks, e.g., by providing additional signals to the hard logic block.

摘要翻译： 公开了用于在集成设备上实现的硬逻辑元件和软逻辑元件之间的接口的系统和方法。 特别地，提供了包括硬逻辑和软逻辑之间的互连的可配置接口，其使信号能够在硬逻辑块和软逻辑模块的输入和输出之间选择性地路由。 互连允许绕过某些硬逻辑块以有利于软逻辑功能。 此外，互连允许软逻辑来增加硬逻辑块的处理，例如通过向硬逻辑块提供附加信号。

公开(公告)号：US20060080467A1

公开(公告)日：2006-04-13

申请号：US10927967

申请日：2004-08-26

申请人： Stephen Gould ,  Ernest Peltzer ,  Sean Clift ,  Kellie Marks ,  Robert Barrie

发明人： Stephen Gould ,  Ernest Peltzer ,  Sean Clift ,  Kellie Marks ,  Robert Barrie

IPC分类号： G06F15/16

CPC分类号： G06F9/5005 ,  G06F2209/509

摘要： Incoming data streams are processed at relatively high speed for decoding, content inspection and classification. A multitude of processing channels process multiple data streams concurrently so as to allows networking based host systems to provide the data streams—as the packets carrying these data streams are received from the network—without requiring the data streams to be buffered. Moreover, host systems processing stored content, such as email messages and computer files, can process more than one stream at once and thereby make better utilization of the host system's CPU. Processing bottlenecks are alleviated by offloading the tasks of data extraction, inspection and classification from the host CPU. A content processing system which so processes the incoming data streams, is readily extensible to accommodate and perform additional data processing algorithms. The content processing system is configurable to enable additional data processing algorithms to be performed in parallel or in series.

摘要翻译： 进入数据流以相对高的速度进行处理，用于解码，内容检查和分类。 多个处理通道同时处理多个数据流，以便允许基于网络的主机系统提供数据流，因为从网络接收携带这些数据流的分组，而不需要缓冲数据流。 此外，处理诸如电子邮件消息和计算机文件的存储内容的主机系统可以一次处理多个流，从而更好地利用主机系统的CPU。 通过从主机CPU卸载数据提取，检查和分类的任务，可以减轻处理瓶颈。 处理输入数据流的内容处理系统易于扩展以适应并执行附加的数据处理算法。 内容处理系统可配置为使得能够并行或串行地执行附加数据处理算法。