公开(公告)号：US08060729B1

公开(公告)日：2011-11-15

申请号：US12244904

申请日：2008-10-03

申请人： Steven Perry ,  Martin Roberts ,  Kellie Marks

发明人： Steven Perry ,  Martin Roberts ,  Kellie Marks

IPC分类号： G06F9/00

CPC分类号： G06F15/7892

摘要： In the provided architecture, one or more multi-threaded processors may be combined with hardware blocks having increased functionality. Each hardware block may be able to transfer a data packet to a particular hardware block based on the packet being processing. One or more hardware block may also be able to divide packets into subpackets for separate processing, and other hardware blocks may be able to rejoin the subpackets. Hardware blocks may also be able to transfer packet information between other hardware blocks during the processing sequence.

摘要翻译： 在所提供的架构中，一个或多个多线程处理器可以与具有增加的功能的硬件块组合。 每个硬件块可能能够基于正在处理的分组将数据分组传送到特定的硬件块。 一个或多个硬件块还可能能够将分组划分为子分组以进行单独处理，并且其他硬件块可能能够重新加入子分组。 硬件块也可以在处理序列期间在其它硬件块之间传送分组信息。

公开(公告)号：US20080236030A1

公开(公告)日：2008-10-02

申请号：US11997827

申请日：2006-08-01

申请人： Martin Roberts ,  Christine Ann Blundell ,  Anthony Finn

发明人： Martin Roberts ,  Christine Ann Blundell ,  Anthony Finn

IPC分类号： C10L1/18 ,  C07C53/00

CPC分类号： C10L1/1983 ,  C07C67/08 ,  C07C69/593 ,  C08G63/52 ,  C10L1/191 ,  C10L1/198 ,  C10L10/08

摘要： The invention provides a fuel additive compound represented by the general formula (I) wherein n is zero or an integer from 1 to 20 and in each succinic acid moiety one of R1 and R3 is a C3—C80 internal olefin moiety, and the other of R1 and R3 is hydrogen. Additive compositions containing such compounds have low viscosity and are useful in increasing the lubricity of middle distillate fuels.

摘要翻译： 本发明提供一种由通式（I）表示的燃料添加剂化合物，其中n为0或1至20的整数，并且在每个琥珀酸部分中R 1和R 3中的一个为 / SUP>是C 3 -C 80内烯烃部分，R 1和R 3中的另一个 >是氢。 含有这些化合物的添加剂组合物具有低粘度，并且可用于增加中间馏分燃料的润滑性。

公开(公告)号：US20060237847A1

公开(公告)日：2006-10-26

申请号：US11427746

申请日：2006-06-29

申请人： Martin Roberts ,  Sanh Tang

发明人： Martin Roberts ,  Sanh Tang

IPC分类号： H01L23/52

CPC分类号： H01L27/10882 ,  H01L21/76838 ,  H01L23/485 ,  H01L27/11 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming an electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline silicon layer and the patterning and etching of same to form a via. The via is formed in the first polycrystalline silicon layer to expose the substrate and a second polycrystalline silicon layer is formed in the via to contact the substrate. Portions of the second polycrystalline silicon layer overlying the first polycrystalline silicon layer are removed eliminating any horizontal interface between the two polycrystalline silicon layers. The first polycrystalline silicon layer remaining after the etch is then patterned to form an electrical interconnect.

摘要翻译： 用于形成覆盖衬底的掩埋接触区域的电互连的方法的特征在于沉积第一多晶硅层及其图案化和蚀刻以形成通孔。 通孔形成在第一多晶硅层中以露出衬底，并且在通孔中形成第二多晶硅层以接触衬底。 去除覆盖在第一多晶硅层上的第二多晶硅层的部分，消除了两个多晶硅层之间的任何水平界面。 然后在蚀刻之后残留的第一多晶硅层被图案化以形成电互连。

公开(公告)号：US6009075A

公开(公告)日：1999-12-28

申请号：US625801

申请日：1996-03-29

申请人： Martin Roberts ,  Thomas A. Potter ,  R. Douglas Howson, Jr.

发明人： Martin Roberts ,  Thomas A. Potter ,  R. Douglas Howson, Jr.

IPC分类号： H04J3/08 ,  H04J3/14 ,  H04J3/16 ,  H04Q11/04 ,  H04L12/24

CPC分类号： H04J3/1611 ,  H04J3/085 ,  H04J3/14 ,  H04Q11/0478 ,  H04J2203/0042 ,  H04J2203/006 ,  H04J2203/0089 ,  Y10S370/907

摘要： A transport interface (10) provides add drop multiplex functionality and termination requirements for the transportation of network traffic. The transport interface (10) includes high speed units (12), broadband interfaces (16), and SONET formatters (18). Each high speed unit (12), broadband interface (16), and SONET formatter has redundant protection pairs (A and B). The high speed units (12), broadband interfaces (16), and SONET formatters (18) communicate with each other by in-band datalinks (40). The redundant protection pairs (A and B) communicate with one another by protection pair datalinks (42). The in-band datalinks (40) and the protection pair datalinks (42) provide an effective means for performing protection switching within the transport interface (10) in the event of component failure. The in-band datalinks (40) are generated out of available or consumed bytes within either a section overhead (32) or a line overhead (34) of SONET OC-N frame (30). The protection pair datalinks (42) provide communication capability over a common control communications interface. The in-band datalinks (40) and the protection pair data links (42) work together to provide a smooth transition from one component to another in the event of a protection switch.

摘要翻译： 传输接口（10）为网络流量的传输提供添加分支复用功能和终止要求。 传输接口（10）包括高速单元（12），宽带接口（16）和SONET格式化器（18）。 每个高速单元（12），宽带接口（16）和SONET格式化器具有冗余保护对（A和B）。 高速单元（12），宽带接口（16）和SONET格式化器（18）通过带内数据链路（40）彼此通信。 冗余保护对（A和B）通过保护对数据链路彼此通信（42）。 带内数据链路（40）和保护对数据链路（42）提供了在组件故障的情况下在传输接口（10）内执行保护切换的有效手段。 在SONET OC-N帧（30）的段开销（32）或行开销（34）之内，可用或消耗的字节产生带内数据链路（40）。 保护对数据链路（42）通过公共控制通信接口提供通信能力。 在保护开关的情况下，带内数据链路（40）和保护对数据链路（42）一起工作以提供从一个组件到另一个组件的平滑过渡。

公开(公告)号：US5253254A

公开(公告)日：1993-10-12

申请号：US761492

申请日：1991-09-18

申请人： Martin Roberts ,  David L. Manley

发明人： Martin Roberts ,  David L. Manley

IPC分类号： H03M9/00 ,  H04J3/06 ,  H04L7/00 ,  H04L7/08

CPC分类号： H04J3/0608

摘要： A high-speed communication system (32) comprises a serial-to-parallel converter (38) for arbitrary converting a stream of serial data to a stream of arbitrarily aligned parallel data. A pattern detector (44) is coupled to the serial-to-parallel converter (38) for detecting a predetermined pattern from the stream of parallel data and generating a phase signal responsive to the detection of the pattern. An aligner (42) coupled to the pattern detector (44) generates an aligned stream of parallel data responsive to the phase signal.

公开(公告)号：US08761188B1

公开(公告)日：2014-06-24

申请号：US12150889

申请日：2008-04-30

申请人： Anargyros Krikelis ,  Martin Roberts

发明人： Anargyros Krikelis ,  Martin Roberts

IPC分类号： G06F15/76

CPC分类号： G06F15/7896

摘要： In the provided architecture, one or more multi-threaded processors may be combined with hardware blocks. The resulting combination allows for data packets to undergo a processing sequence having the flexibility of software programmability with the high-performance of dedicated hardware. For example, a multi-threaded processor can control the high-level tasks of a processing sequence, while the computationally intensive events (e.g., signal processing filters, matrix operations, etc.) are handled by dedicated hardware blocks.

摘要翻译： 在所提供的架构中，一个或多个多线程处理器可以与硬件块组合。 所得到的组合允许数据分组经历具有与专用硬件的高性能的软件可编程性的灵活性的处理顺序。 例如，多线程处理器可以控制处理序列的高级任务，而计算密集型事件（例如，信号处理过滤器，矩阵操作等）由专用硬件块来处理。

公开(公告)号：US20140067723A1

公开(公告)日：2014-03-06

申请号：US13800053

申请日：2013-03-13

申请人： Boris Katsevman ,  Martin Roberts

发明人： Boris Katsevman ,  Martin Roberts

IPC分类号： G06Q30/02

CPC分类号： G06Q30/0283

摘要： A method includes, in a network of interconnected computers, each of the computers including at least a processor and a memory, receiving in a server linked to the network a set of specifications to meet a requester's language translation needs, the set generated in a client system linked to the network or directly in the server via an appropriate User Interface, in the server, receiving one or more documents from the client system, in the server, analyzing the received set of specifications and the received one or more documents, in the server, generating a tentative optimum translation service solution for the requester according to the analyzed set of specifications, in the server, organizing the most effective translation process suitable to the requester's specifications, and in the server, returning one or more translated documents to the requester in an acceptable format.

摘要翻译： 一种方法包括在互连计算机的网络中，每个计算机至少包括处理器和存储器，在链接到网络的服务器中接收一组规范以满足请求者的语言翻译需要，在客户端中生成的集合 系统通过适当的用户界面，在服务器中直接链接到服务器中，从服务器中接收来自客户端系统的一个或多个文档，分析所接收的一组规格和所接收的一个或多个文档，在 服务器，根据分析的规格集在服务器中为请求者生成暂定的最佳翻译服务解决方案，组织适合请求者规范的最有效的翻译过程，在服务器中，将一个或多个翻译文档返回给请求者 以可接受的格式。

公开(公告)号：USD562036S1

公开(公告)日：2008-02-19

申请号：US29277637

申请日：2007-03-05

申请人： Martin Roberts

设计人： Martin Roberts

公开(公告)号：US20050009280A1

公开(公告)日：2005-01-13

申请号：US10914825

申请日：2004-08-09

申请人： Fred Fishburn ,  Martin Roberts

发明人： Fred Fishburn ,  Martin Roberts

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L39/22

CPC分类号： H01L21/31053 ,  H01L21/32139 ,  H01L21/82345 ,  H01L21/823828 ,  H01L21/823842 ,  Y10S438/941

摘要： The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative capping layer which is formed over a conductive gate layer formed over a substrate. The etch stop layer, the insulative capping layer, and the conductive gate layer are patterned and etched to form a first set of conductive gate constructions over the substrate. A dielectric material is formed and planarized over the first set of gate constructions. Thereafter, the insulative capping layer and the conductive gate layer are patterned and etched to form a second set of conductive gate constructions over the substrate. Other aspects and implementations are contemplated.

公开(公告)号：US5867543A

公开(公告)日：1999-02-02

申请号：US625716

申请日：1996-03-29

申请人： Martin Roberts ,  Thomas A. Potter

发明人： Martin Roberts ,  Thomas A. Potter

IPC分类号： H04J3/06 ,  H04Q11/04

CPC分类号： H04J3/0602 ,  H04J2203/0089 ,  Y10S370/914 ,  Y10S370/916

摘要： A multi-rate transmission system (10) includes a receive section (12) and a transmit section (14). The receive section includes a receiver (16), a clock recovery unit (18), and a serial to parallel converter (20) all operating at a first clock rate (M). The receiver (16) also has a frame recovery unit (22) that operates at any of a plurality of clock rates, including the first clock rate (M) and a second clock rate (M/n). When the frame recovery unit operates at the first clock rate (M), frame information received by the receiver section (12) has unique bits occupying each bit position associated with each clock pulse of the first clock rate (M). When the frame recovery unit (22) operates at the second clock rate (M/n), each unique bit of the frame information occupies a number of bit positions according to a ratio of the first clock rate (M) to the second clock rate (M/n). Similar operation occurs with respect to a frame formatter (30) in the transmit section (14) of the multi-rate transmission system (10).

摘要翻译： 多速率传输系统（10）包括接收部分（12）和传输部分（14）。 接收部分包括全部以第一时钟速率（M）操作的接收器（16），时钟恢复单元（18）和串行到并行转换器（20）。 接收机（16）还具有帧恢复单元（22），其以包括第一时钟速率（M）和第二时钟速率（M / n）的多个时钟速率中的任何一个操作。 当帧恢复单元以第一时钟速率（M）操作时，由接收器部分（12）接收的帧信息具有占据与第一时钟速率（M）的每个时钟脉冲相关联的每个位位置的唯一位。 当帧恢复单元（22）以第二时钟速率（M / n）操作时，帧信息的每个唯一位根据第一时钟速率（M）与第二时钟速率（M）的比率占用多个比特位置 （M / n）。 对于多速率传输系统（10）的发送部分（14）中的帧格式器（30），发生相似的操作。