公开(公告)号：US4689785A

公开(公告)日：1987-08-25

申请号：US775565

申请日：1985-09-13

Applicant: Kenji Toyonaga ,  Yoshihito Higashitsutsumi ,  Akihiro Yanai

Inventor： Kenji Toyonaga ,  Yoshihito Higashitsutsumi ,  Akihiro Yanai

IPC: H04L12/407 ,  H04J3/02 ,  H04J3/24

CPC classification number: H04L47/10 ,  H04L12/407

Abstract: A data transmission system having a plurality of stations and bus structure connected among the stations for sending an information data or an answer back data in a packet from one station to another station through the bus structure. Each station has a receiver which receives the packet and detects that the packet of information data is directed to the station by identifying the address data. If it is so detected that the packet is directed to this station, an acknowledge signal is produced. A carrier sensor is provided for producing a presence signal indicative of the presence of the packet on the bus structure. A counter starts to count time when the presence signal disappears, and produces first and second time-up signals after the lapse of first and second predetermined times, respectively, provided that the first predetermined time is shorter than the second predetermined time. A transmitter prepares the packet of answer back data in response to the receipt of the acknowledge signal and transmits the prepared answer back data after the counter has counted the first predetermined time and before the end of the second predetermined time.

Abstract translation: 一种数据传输系统，具有连接在各站之间的多个站和总线结构，用于通过总线结构从一个站向另一站发送数据包中的信息数据或答复数据。 每个站具有接收分组并且通过识别地址数据来检测信息数据分组被引导到站的接收机。 如果检测到分组被引导到该站，则产生确认信号。 提供载波传感器用于产生表示在总线结构上存在分组的存在信号。 当存在信号消失时，计数器开始计数时间，并且如果第一预定时间短于第二预定时间，则分别在经过第一和第二预定时间之后产生第一和第二时间信号。 响应于接收到确认信号，发射机准备回答数据包，并在计数器计数第一预定时间之后并在第二预定时间结束之前发送准备的应答数据。

公开(公告)号：US4667338A

公开(公告)日：1987-05-19

申请号：US739781

申请日：1985-05-31

Applicant: Kenji Toyonaga ,  Yoshihito Higashitsutsumi ,  Akihiro Yanai ,  Toru Akiyama

Inventor： Kenji Toyonaga ,  Yoshihito Higashitsutsumi ,  Akihiro Yanai ,  Toru Akiyama

IPC: H03K5/1252 ,  H03K23/00

CPC classification number: H03K5/1252

Abstract: A noise elimination circuit for eliminating noise signals from data given by a binary form includes a modulo in up/down counter having a first input for receiving binary data, a second input for receiving clock pulses and output for producing a counted signal. The counter is effected to count up in response to the clock pulses when the binary data is a HIGH, and to count down in response to said clock pulses when the binary data is a LOW. A decoder is provided which has inputs for receiving the counted signal, a first output for producing an indication signal when the counted signal corresponds to a first predetermined number i, and a second output for producing an indication signal when the counted signal corresponds to a second predetermined number j, in which i is equal to or greater than zero, j is greater than i and n is equal to or greater than j. A flip-flop is provided which has a reset terminal connected to the first output of the decoder, a set terminal connected to the second output of the decoder and an output for producing a data with noise signals being eliminated.

Abstract translation: 用于从由二进制形式给出的数据中消除噪声信号的噪声消除电路包括具有用于接收二进制数据的第一输入的上/下计数器模块，用于接收时钟脉冲的第二输入和用于产生计数信号的输出。 当二进制数据为高电平时，计数器响应于时钟脉冲进行计数，并且当二进制数据为低电平时响应于所述时钟脉冲递减计数。 提供了一种解码器，其具有用于接收计数信号的输入端，当计数信号对应于第一预定数量i时产生指示信号的第一输出端和用于当计数信号对应于第二预定数量值时产生指示信号的第二输出端 预定数量j，其中i等于或大于零，j大于i且n等于或大于j。 提供了一种触发器，其具有连接到解码器的第一输出的复位端子，连接到解码器的第二输出端的设置端子和用于产生具有噪声信号的数据的输出被消除。