公开(公告)号：US20120055130A1

公开(公告)日：2012-03-08

申请号：US13223068

申请日：2011-08-31

申请人： Kenneth Au ,  Richard J. Gilpatrick ,  Steven C. Crouch

发明人： Kenneth Au ,  Richard J. Gilpatrick ,  Steven C. Crouch

IPC分类号： A01D34/00

CPC分类号： A01D43/14

摘要： A lawn mower and spreader system includes a deck, a hopper, and a spreading element. The deck supports an engine having a power takeoff and at least partially surrounds a blade coupled to the power takeoff. The hopper is configured to support granular fertilizer. Furthermore, the hopper has a discharge chute leading to an opening in the deck. The spreading element is coupled to the power takeoff of the engine and is positioned between the deck and the blade. The spreading element includes a hub and arms that extend laterally from hub. The arms are spaced apart from one another by open slots.

摘要翻译： 割草机和撒布机系统包括甲板，料斗和铺展元件。 甲板支撑具有动力输出的发动机，并且至少部分地围绕与动力输出相连的叶片。 料斗配置为支撑颗粒肥料。 此外，料斗具有通向甲板上的开口的卸料槽。 扩散元件耦合到发动机的动力输出并且位于甲板和叶片之间。 扩展元件包括从轮毂横向延伸的轮毂和臂。 臂通过开放的槽彼此间隔开。

公开(公告)号：US06117730A

公开(公告)日：2000-09-12

申请号：US427402

申请日：1999-10-25

申请人： Hideki Komori ,  Kenneth Au ,  Mark Ramsbey

发明人： Hideki Komori ,  Kenneth Au ,  Mark Ramsbey

IPC分类号： H01L21/8246 ,  H01L21/8247

CPC分类号： H01L27/11568 ,  H01L27/11526 ,  H01L27/11546 ,  Y10S438/954

摘要： A process for fabricating an ONO structure for a MONOS type Flash cell having a core and a periphery includes providing a semiconductor substrate. A first silicon oxide layer is grown overlying the semiconductor substrate, and a silicon nitride layer is deposited overlying the silicon oxide layer. Before depositing a second silicon oxide layer of the ONO structure, a bit-line mask is performed for forming at least one bit-line at the core. Thereafter, an ONO mask is formed to protect the ONO structure during an etch of the periphery. After depositing and cleaning the masks for the bit-line formation and the periphery etch, the second silicon oxide layer is deposited to overlie the silicon nitride layer using an HTO deposition process. By depositing the second silicon oxide layer after forming the ONO and bit-line masks, degradation of the second silicon oxide layer is prevented, and the top silicon oxide layer maintains a high quality.

摘要翻译： 用于制造具有芯和外围的MONOS型闪存单元的ONO结构的工艺包括提供半导体衬底。 生长在半导体衬底上的第一氧化硅层，并且沉积氮化硅层覆盖在氧化硅层上。 在沉积ONO结构的第二氧化硅层之前，执行位线掩模以在芯处形成至少一个位线。 此后，形成ONO掩模以在周边蚀刻期间保护ONO结构。 在沉积和清洁用于位线形成和外围蚀刻的掩模之后，使用HTO沉积工艺沉积第二氧化硅层以覆盖氮化硅层。 通过在形成ONO和位线掩模之后沉积第二氧化硅层，防止第二氧化硅层的劣化，并且顶部氧化硅层保持高质量。

公开(公告)号：US06319775B1

公开(公告)日：2001-11-20

申请号：US09433037

申请日：1999-10-25

申请人： Arvind Halliyal ,  Robert B. Ogle ,  Susan G. Kim ,  Kenneth Au

发明人： Arvind Halliyal ,  Robert B. Ogle ,  Susan G. Kim ,  Kenneth Au

IPC分类号： H01L218247

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L21/3144 ,  H01L29/66833

摘要： A process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device includes the formation of a nitrogenated top oxide layer. The process includes the sequential formation of a silicon nitride layer and a top oxide layer using an in-situ LPCVD or RTCVD deposition process in which the silicon nitride layer is not exposed to ambient atmosphere prior to the formation of the top oxide layer. After forming the top oxide layer, an annealing process is carried out to diffuse nitrogen into the top oxide layer. The formation of a nitrogenated top oxide layer provides an improved two-bit EEPROM memory device by reducing charge leakage in the ONO floating-gate electrode.

摘要翻译： 在2位EEPROM器件中制造ONO浮栅电极的工艺包括形成氮化的顶部氧化物层。 该方法包括使用原位LPCVD或RTCVD沉积工艺顺序地形成氮化硅层和顶部氧化物层，其中氮化硅层在形成顶部氧化物层之前不暴露于环境大气。 在形成顶部氧化物层之后，进行退火处理以将氮扩散到顶部氧化物层中。 氮化顶部氧化物层的形成通过减少ONO浮栅电极中的电荷泄漏来提供改进的两位EEPROM存储器件。

公开(公告)号：US06265268B1

公开(公告)日：2001-07-24

申请号：US09426672

申请日：1999-10-25

申请人： Arvind Halliyal ,  Robert B. Ogle ,  Hideki Komori ,  Kenneth Au

发明人： Arvind Halliyal ,  Robert B. Ogle ,  Hideki Komori ,  Kenneth Au

IPC分类号： H01L218247

CPC分类号： H01L29/7923 ,  H01L21/28282

摘要： A process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device includes the formation of a top oxide layer using a high-temperature-oxide (HTO) deposition process in which the HTO process is carried out at a temperature of about 700 to about 800° C. by either an LPCVD or RTCVD deposition processor. The process further includes the sequential formation of a silicon nitride layer and a top oxide layer using an in-situ LPCVD or RTCVD deposition process in which the silicon nitride layer is not exposed to ambient atmosphere prior to the formation of the top oxide layer. The formation of the top oxide layer using an HTO deposition process provides an improved two-bit EEPROM memory device by reducing charge leakage in the ONO floating-gate electrode.

摘要翻译： 用于在2位EEPROM器件中制造ONO浮栅电极的工艺包括使用高温氧化物（HTO）沉积工艺形成顶部氧化物层，其中HTO工艺在约 通过LPCVD或RTCVD沉积处理器700至约800℃。 该方法还包括使用原位LPCVD或RTCVD沉积工艺顺序地形成氮化硅层和顶部氧化物层，其中氮化硅层在形成顶部氧化物层之前不暴露于环境大气中。 使用HTO沉积工艺形成顶部氧化物层通过减少ONO浮栅电极中的电荷泄漏来提供改进的两位EEPROM存储器件。

公开(公告)号：US06207502B1

公开(公告)日：2001-03-27

申请号：US09426255

申请日：1999-10-25

申请人： Kenneth Au ,  David K. Foote ,  Steven K. Park ,  Fei Wang ,  Bharath Rangarajan

发明人： Kenneth Au ,  David K. Foote ,  Steven K. Park ,  Fei Wang ,  Bharath Rangarajan

IPC分类号： H01L218247

CPC分类号： H01L27/11568

摘要： A process for fabricating a MONOS type Flash cell device having a periphery field oxide region and a bit-line region includes providing a semiconductor substrate and growing a barrier silicon oxide layer to overlie semiconductor substrate. Thereafter, a thick silicon nitride layer is formed to overlie the barrier silicon oxide layer. A mask and etch are performed at the periphery of the MONOS type cell to form a trench in the semiconductor substrate. The periphery field oxide region is formed by depositing silicon oxide to fill the trench. Thereafter, a mask and etch are performed at the core of the MONOS cell to form a trench in the semiconductor substrate. The bit-line oxide region is formed by depositing silicon oxide to fill the trench. Thereafter, the thick silicon nitride layer is removed. Since the periphery field oxide region and bit-line region are formed before the thick nitride layer is removed, the formation of an unwanted bird's beak is reduced.

摘要翻译： 一种制造具有外围场氧化物区域和位线区域的MONOS型闪存单元器件的工艺包括：提供半导体衬底并生长覆盖半导体衬底的势垒氧化硅层。 此后，形成厚的氮化硅层以覆盖阻挡氧化硅层。 在MONOS型电池的外围进行掩模和蚀刻，以在半导体衬底中形成沟槽。 通过沉积氧化硅以填充沟槽而形成外围场氧化物区域。 此后，在MONOS单元的核心处进行掩模和蚀刻，以在半导体衬底中形成沟槽。 位线氧化物区域通过沉积氧化硅以填充沟槽而形成。 此后，去除厚的氮化硅层。 由于在去除厚氮化物层之前形成外围场氧化物区域和位线区域，所以不希望的鸟喙形成减少。

公开(公告)号：US06180538B2

公开(公告)日：2001-01-30

申请号：US09426240

申请日：1999-10-25

申请人： Arvind Halliyal ,  Robert B. Ogle ,  Kenneth Au ,  Steven K. Park

发明人： Arvind Halliyal ,  Robert B. Ogle ,  Kenneth Au ,  Steven K. Park

IPC分类号： H01L2131

CPC分类号： H01L29/7923 ,  H01L21/28282 ,  H01L21/3143

摘要： A process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device includes the formation of a first and second oxide layers using a high-temperature-oxide (HTO) deposition process in which the HTO process is carried out at a temperature of about 700 to about 800° C. The process further includes the sequential formation of a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer using an RTCVD process in which the silicon nitride layer is not exposed to ambient atmosphere prior to the formation of the top oxide layer. The formation of the first and second oxide layers using an RTCVD process provides an improved two-bit EEPROM memory device by reducing charge leakage in the ONO floating-gate electrode.

摘要翻译： 用于在2位EEPROM器件中制造ONO浮栅电极的工艺包括使用高温氧化物（HTO）沉积工艺形成第一和第二氧化物层，其中HTO工艺在温度 约700至约800℃。该方法还包括使用其中氮化硅层不暴露于环境大气的RTCVD工艺来顺序地形成第一氧化硅层，氮化硅层和第二氧化硅层 在形成顶部氧化物层之前。 使用RTCVD工艺形成第一和第二氧化物层通过减少ONO浮栅电极中的电荷泄漏来提供改进的两位EEPROM存储器件。