公开(公告)号：US07504589B2

公开(公告)日：2009-03-17

申请号：US10972829

申请日：2004-10-25

申请人： Kenneth P. Parker ,  Chris R. Jacobsen

发明人： Kenneth P. Parker ,  Chris R. Jacobsen

IPC分类号： H05K1/00

CPC分类号： G01R31/2818 ,  H05K1/0268 ,  H05K3/3452 ,  H05K3/3457 ,  H05K2203/0278 ,  H05K2203/043

摘要： A test access point structure for accessing test points of a printed circuit board and method of fabrication thereof is presented. Each test access point structure is conductively connected to a trace at a test access point and above an exposed surface of the printed circuit board to be accessible for probing by a fixture probe. The test access point structure may be designed and manufactured to permit deformation of the test access point structure upon initial probing of the test access point structure with a fixture probe to ensure electrical contact between the fixture probe and the test access point structure.

摘要翻译： 介绍了一种用于访问印刷电路板测试点的测试接入点结构及其制造方法。 每个测试接入点结构导电地连接到测试接入点处的迹线并且在印刷电路板的暴露表面上方，以便通过夹具探针探测。 可以设计和制造测试接入点结构，以便在使用夹具探针初次探测测试接入点结构时，允许测试接入点结构发生变形，以确保夹具探头与测试接入点结构之间的电接触。

公开(公告)号：US07437638B2

公开(公告)日：2008-10-14

申请号：US10292267

申请日：2002-11-12

申请人： Kenneth P. Parker

发明人： Kenneth P. Parker

IPC分类号： G01R31/28

CPC分类号： G01R31/318577 ,  G01R31/318547 ,  G01R31/318572

摘要： Disclosed herein are various methods and apparatus related to Boundary-Scan testing, including a method for generating Boundary-Scan test vectors. The method assigns different binary signatures to all of the drivers and hysteretic test receiver memories of a circuit assembly under test, and then generates a series of Boundary-Scan test vectors wherein each test vector is derived from corresponding bits of the binary signatures.

摘要翻译： 本文公开了与边界扫描测试相关的各种方法和装置，包括用于产生边界扫描测试向量的方法。 该方法为测试中的电路组件的所有驱动器和滞后测试接收器存储器分配不同的二进制签名，然后生成一系列边界扫描测试向量，其中每个测试向量从二进制签名的相应位导出。

公开(公告)号：US07362106B2

公开(公告)日：2008-04-22

申请号：US11170365

申请日：2005-06-29

申请人： Kenneth P. Parker ,  Myron J. Schneider

发明人： Kenneth P. Parker ,  Myron J. Schneider

IPC分类号： G01R31/08 ,  G01R27/26 ,  G01R31/302 ,  G01R31/04

CPC分类号： G01R31/312

摘要： A method and apparatus for detecting open defects on non-probed node under test of an electrical device using capacitive lead frame technology is presented. In accordance with the method of the invention, a probed node neighboring the non-probed node under test is stimulated with a known source signal. A sensor of a capacitive sensing probe is capacitively coupled to at least the probed node and non-probed node under test of the electrical device, and a measuring device coupled to the capacitive sensing probe measures a capacitively coupled signal present between the sensor of the probe and at least the probed and non-probed node of the electrical device. Based on the value of the capacitively sensed signal, a known expected “defect-free” capacitively sensed signal measurement and/or a known expected “open” capacitively sensed signal measurement, a determination is made of whether an open defect exists on the non-probed node under test of the electrical device.

摘要翻译： 提出了一种使用电容引线框架技术在电气设备测试下检测非探测节点上的开放缺陷的方法和装置。 根据本发明的方法，用已知的源信号来刺激与被测探测的非探测节点相邻的探测节点。 电容式感测探头的传感器电容耦合到至少被电气设备测试的探测节点和非探测节点，并且耦合到电容感测探头的测量装置测量存在于探针传感器之间的电容耦合信号 以及至少探测和未探测的电气设备的节点。 基于电容感测信号的值，已知的预期的“无缺陷”电容感测信号测量和/或已知的预期“开放”电容感测信号测量，确定在非易失性存储器 被检测的电气设备节点。

公开(公告)号：US07187165B2

公开(公告)日：2007-03-06

申请号：US11010074

申请日：2004-12-10

申请人： Chris R. Jacobsen ,  Kenneth P. Parker ,  John E. Herczeg

发明人： Chris R. Jacobsen ,  Kenneth P. Parker ,  John E. Herczeg

IPC分类号： G01R31/02 ,  G01R31/28 ,  G06F17/50

CPC分类号： G01R31/2818 ,  H05K1/0268 ,  H05K3/0005

摘要： Techniques for automating test pad insertion in a printed circuit board (PCB) design and fixture probe insertion in a PCB tester fixture are presented. A probe location algorithm predictably determines respective preferred probing locations from among respective sets of potential probing locations associated with a number of respective nets in a PCB design. Test pads, preferably in the form of bead probes, are added to the PCB design at the respective preferred probing locations along with, where feasible, one or more alternate probing locations chosen from among remaining ones of the respective sets of potential probing locations. During fixture design, nets with multiple test pads implemented in the PCB design are processed by the same probe location algorithm used during PCB design to determine the associated preferred and alternate probing locations for said respective nets. Fixture probes are preferably inserted in the PCB tester fixture design at respective preferred probing locations such that tips of said respective fixture probes exactly align with corresponding preferred test pads of a PCB implemented in accordance with the PCB design should the PCB be mounted in a printed circuit board tester fixture implemented in accordance with the PCB tester fixture design.

摘要翻译： 介绍了在印刷电路板（PCB）设计中自动化测试垫插入和PCB测试仪夹具中夹具探针插入的技术。 探针定位算法可预测地确定与PCB设计中的多个相应网络相关联的各组潜在探测位置中的各个优选探测位置。 优选地以珠探针的形式的测试垫在相应的优选探测位置附加到PCB设计中，并且在可行的情况下，从相应的潜在探测位置集合中的剩余的探测位置中选择一个或多个替代探测位置。 在夹具设计期间，在PCB设计中实现的具有多个测试焊盘的网络通过在PCB设计期间使用的相同探针位置算法来处理，以确定用于所述各个网络的相关联的优选和替代探测位置。 夹具探针优选地以相应的优选探测位置插入到PCB测试器夹具设计中，使得如果将PCB安装在印刷电路中，则所述相应夹具探针的尖端与根据PCB设计实现的PCB的相应优选测试垫精确对准 按照PCB测试仪器设计实现板测试仪。

公开(公告)号：US07161369B2

公开(公告)日：2007-01-09

申请号：US10978100

申请日：2004-10-29

申请人： Kenneth P. Parker ,  Richard W. Rivas, Sr.

发明人： Kenneth P. Parker ,  Richard W. Rivas, Sr.

IPC分类号： G01R1/067

CPC分类号： G01R1/06722 ,  G01R31/2808 ,  G01R31/2812 ,  H05K1/0268 ,  H05K3/1225 ,  H05K2203/043

摘要： A method and apparatus for a wiping fixture probe for cleaning oxides, residues or other contaminants from the surface of a solder bead probe and probing a solder bead probe on a printed circuit board during in-circuit testing.

摘要翻译： 一种擦拭夹具探针的方法和装置，用于在电路测试期间从焊珠探针的表面清洁氧化物，残留物或其它污染物并在印刷电路板上探测焊珠探针。

公开(公告)号：US5513188A

公开(公告)日：1996-04-30

申请号：US208245

申请日：1994-03-09

申请人： Kenneth P. Parker ,  Kenneth E. Posse

发明人： Kenneth P. Parker ,  Kenneth E. Posse

IPC分类号： G01R31/02 ,  G01R31/28 ,  G01R31/3183 ,  G01R31/3185 ,  G06F11/22 ,  H04B17/00

CPC分类号： G01R31/318561 ,  G01R31/318307 ,  G01R31/318538 ,  G01R31/31855 ,  G01R31/318566 ,  G06F11/2273

摘要： A method for generating improved detection and diagnostic test patterns and for improving the diagnostic resolution of interconnect testing of a circuit is based on the premise that short-circuits are most likely to result from solder bridges between closely adjacent pins. In a first embodiment, an optimal boundary-scan test pattern is generated. In a second embodiment, boundary-scan test diagnosis is enhanced by utilizing x,y coordinate data corresponding to the physical location of devices on the tested circuit. In a third embodiment, diagnosis of unpowered short-circuit testing is enhanced.

摘要翻译： 用于产生改进的检测和诊断测试模式以及用于提高电路的互连测试的诊断分辨率的方法是基于短路最可能由紧密相邻的引脚之间的焊料桥引起的前提。 在第一实施例中，产生最佳边界扫描测试图案。 在第二实施例中，通过利用与所测试的电路上的设备的物理位置对应的x，y坐标数据来增强边界扫描测试诊断。 在第三实施例中，提高了无动力短路测试的诊断。

公开(公告)号：US5448166A

公开(公告)日：1995-09-05

申请号：US156204

申请日：1993-11-22

申请人： Kenneth P. Parker ,  Kenneth E. Posse

发明人： Kenneth P. Parker ,  Kenneth E. Posse

IPC分类号： G01R31/28 ,  G01R31/3185

CPC分类号： G01R31/318586

摘要： A method for testing a circuit board having both boundary-scan and non-boundary-scan devices is provided. The test method distinguishes boundary-scan nodes from non-boundary-scan nodes and uses cartesian coordinates (X,Y) of every pin of every device on the circuit board to determine a number of sets of non-boundary-scan nodes that are within a predetermined distance "R" from a device pin coupled to a boundary-scan node. The number of sets of non-boundary-scan nodes are grouped into "independent" groups which can be tested in parallel. A test cycle is performed by testing independent non-boundary-scan nodes in parallel by forcing drivers in the boundary-scan devices to a first logic state, and forcing each of the non-boundary-scan nodes to another logic state for a brief interval. Receivers on the boundary-scan devices capture a response vector during the brief interval, which is scanned out of the circuit board for evaluation. The response vector reflects which of the nodes has failed, and cartesian coordinate data giving the precise location of any faulty node(s) is returned to user.

摘要翻译： 提供了一种用于测试具有边界扫描和非边界扫描装置的电路板的方法。 测试方法区分边界扫描节点与非边界扫描节点，并使用电路板上每个设备的每个引脚的笛卡尔坐标（X，Y）来确定多个非边界扫描节点的集合 与耦合到边界扫描节点的设备引脚的预定距离“R”。 非边界扫描节点的数量被分组为可以并行测试的“独立”组。 通过将边界扫描设备中的驱动程序强制为第一逻辑状态并将每个非边界扫描节点强制为另一个逻辑状态以进行短暂间隔来并行测试独立的非边界扫描节点来执行测试周期 。 边界扫描设备上的接收器在短暂的时间间隔内捕获响应向量，该时间间隔被扫描出电路板进行评估。 响应向量反映哪些节点已经失败，并且给出任何故障节点的精确位置的笛卡尔坐标数据被返回给用户。

公开(公告)号：US5387862A

公开(公告)日：1995-02-07

申请号：US88279

申请日：1993-07-06

申请人： Kenneth P. Parker ,  Kenneth E. Posse

发明人： Kenneth P. Parker ,  Kenneth E. Posse

IPC分类号： G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318586

摘要： The (X,Y) positions of the nodes in a circuit containing boundary scan components and non-boundary-scan components are stored in a computer. The computer selects a set of non-boundary scan nodes within a radius R of a selected boundary-scan node, R being the length of solder bridges in the circuit. A logic 0 voltage is applied to the set and a boundary-scan test is performed. If the boundary-scan test fails, a fault is declared in the circuit between the set and the selected boundary-scan node. A logic 1 voltage is applied to one of the nodes in the set, and the test repeated. If the test returns different results, the fault is declared between that one node and the selected boundary-scan node. A time limit is established for each non-boundary scan node corresponding to the length of time a short in that node can be tolerated. The boundary-scan nodes in the circuit are tested in the order of ascending time limits in its associated set. Power is cut off to the circuit if the time limit of a node not yet tested, or tested and failed, is exceeded.

摘要翻译： 包含边界扫描分量和非边界扫描分量的电路中的节点的（X，Y）位置被存储在计算机中。 计算机在所选择的边界扫描节点的半径R内选择一组非边界扫描节点，R是电路中焊料桥的长度。 将逻辑0电压施加到该组，并进行边界扫描测试。 如果边界扫描测试失败，则在设备和所选边界扫描节点之间的电路中声明故障。 将逻辑1电压施加到集合中的一个节点，并重复测试。 如果测试返回不同的结果，则在该一个节点和所选的边界扫描节点之间声明故障。 针对每个非边界扫描节点建立一个时间限制，对应于该节点可以容忍的短时间长度。 电路中的边界扫描节点按照其相关组中的上升时间限制的顺序进行测试。 如果节点尚未测试或测试失败的时间超出，电源将被切断。

公开(公告)号：US07307426B2

公开(公告)日：2007-12-11

申请号：US11179978

申请日：2005-07-12

申请人： Kenneth P. Parker ,  Chris R. Jacobsen

发明人： Kenneth P. Parker ,  Chris R. Jacobsen

IPC分类号： G01R31/02

CPC分类号： G01R31/312

摘要： A method and apparatus for detecting open defects on grounded nodes of an electrical device using capacitive lead frame technology is presented. In accordance with the method of the invention, an accessible signal node that is capacitively coupled the grounded node is stimulated with a known source signal. A capacitive sense plate is capacitively coupled to the stimulated node and grounded node of the electrical device, and a measuring device coupled to the capacitive sense plate capacitively senses a resulting signal. The value of the capacitively sensed signal is indicative of the presence or non-presence of an open defect on one or both of the grounded node and stimulated signal node.

公开(公告)号：US07259576B2

公开(公告)日：2007-08-21

申请号：US11079702

申请日：2005-03-14

申请人： Kenneth P Parker ,  Chris R Jacobsen

发明人： Kenneth P Parker ,  Chris R Jacobsen

IPC分类号： G01R31/08

CPC分类号： G01R1/06722 ,  G01R31/2805

摘要： A twisting fixture probe for cleaning oxides, residues or other contaminants from the surface of a solder bead probe and probing a solder bead probe on a printed circuit board during in-circuit testing.

摘要翻译： 用于在电路测试期间从焊珠探针的表面清洁氧化物，残留物或其他污染物并在印刷电路板上探测焊珠探针的扭转夹具探头。