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    SCAN TOPOLOGY DISCOVERY IN TARGET SYSTEMS
    6.
    发明申请
    SCAN TOPOLOGY DISCOVERY IN TARGET SYSTEMS 审中-公开
    目标系统中的扫描拓扑发现

    公开(公告)号：US20170059653A1

    公开(公告)日：2017-03-02

    申请号：US15348352

    申请日：2016-11-10

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Gary L. Swoboda

    IPC分类号： G01R31/3177 ,  G01R31/317

    CPC分类号： G01R31/3177 ,  G01R31/31701 ,  G01R31/31713 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/318533 ,  G01R31/318538 ,  G01R31/318544 ,  G06F11/22 ,  G06F11/267 ,  G06F11/27 ,  G06F11/36 ,  G06F11/3656 ,  G06F2201/88 ,  H04L43/50

    摘要： Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data input signal and a data output signal of the scan topology. An input data value and an output data value for each of the plurality of components is sampled and recorded. A low logic value is then scanned through the scan path and recorded at each component. The scan topology may be determined based on the recorded data values and the recorded scan values.

    摘要翻译： 可以通过驱动数据输入信号上的低逻辑值和扫描拓扑的数据输出信号来执行具有与扫描拓扑结合的多个分量的目标系统的拓扑发现。 对多个分量中的每一个的输入数据值和输出数据值进行采样和记录。 然后通过扫描路径扫描低逻辑值，并记录在每个组件上。 可以基于记录的数据值和记录的扫描值来确定扫描拓扑。

    Frequency Scaled Segmented Scan Chain for Integrated Circuits
    8.
    发明申请
    Frequency Scaled Segmented Scan Chain for Integrated Circuits 有权
    用于集成电路的频率分段扫描链

    公开(公告)号：US20160266202A1

    公开(公告)日：2016-09-15

    申请号：US14985699

    申请日：2015-12-31

    申请人： Texas Instruments Incorporated

    发明人： Rajesh Kumar Mittal ,  Wilson Pradeep ,  Vivek Singhal

    IPC分类号： G01R31/3177 ,  G01R31/317 ,  G01R31/28

    CPC分类号： G01R31/3177 ,  G01R31/2851 ,  G01R31/31721 ,  G01R31/31725 ,  G01R31/318538 ,  G01R31/318563 ,  G01R31/318575

    摘要： A scan chain may be formed throughout an integrated circuit in which the scan chain includes at least a first segment and a second segment. A first portion of a test pattern is scanned into the first segment by clocking a first scan cell of the first segment with an even clock while clocking a remainder of the plurality of scan cells in the first segment with an odd clock, in which the odd clock is out of phase with the even clock, in which the even clock and odd clock have a rate equal to a scan rate of the test pattern divided by an integer N. A second portion of the test pattern is scanned into the second segment by clocking the plurality of scan cells in the second segment with the odd clock, such that the second portion of the test pattern is not scanned into the first segment.

    摘要翻译： 扫描链可以形成在整个集成电路中，其中扫描链包括至少第一段和第二段。 通过以奇数时钟对第一段中的多个扫描单元的其余部分进行计时，同时以奇数时钟计时第一段的第一扫描单元，将测试图案的第一部分扫描到第一段中，其中奇数 时钟与偶数时钟异相，其中偶数时钟和奇数时钟具有等于测试图案的扫描速率除以整数N的速率。测试图案的第二部分被扫描到第二段中 以奇数时钟对第二段中的多个扫描单元进行计时，使得测试图案的第二部分不被扫描到第一段中。