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公开(公告)号:US5794181A
公开(公告)日:1998-08-11
申请号:US824072
申请日:1997-03-24
申请人: Gerard Benbassat , Frank L. Laczko, Sr. , Stephen H. Li , Kenneth R. Cyr , Jonathan L. Rowlands
发明人: Gerard Benbassat , Frank L. Laczko, Sr. , Stephen H. Li , Kenneth R. Cyr , Jonathan L. Rowlands
摘要: A data processing system (10) is disclosed which comprises a microprocessor host (12) coupled to a decoding system (14). A host interface block (18) receives a bit stream and passes bit stream on to a system decoder block (20). The system decoder block (20) extracts the appropriate data from the bit stream and loads an input buffer (24) or an optional external buffer (26). An audio decoder block (28) retrieves the data from the input buffer (24) and generates scale factor indices, bit per code word values and subband samples which are stored in an arithmetic unit buffer (30). A hardware filter arithmetic unit block (32) retrieves the information from the arithmetic unit buffer (30) and dequantizes, transforms and filters the data to generate PCM output data which is loaded into a PCM buffer (34). The data within the PCM buffer (34) is output by a PCM output block (36) to a digital-to-analog converter (16).
摘要翻译: 公开了一种数据处理系统(10),其包括耦合到解码系统(14)的微处理器主机(12)。 主机接口块(18)接收比特流并将比特流传送到系统解码器块(20)。 系统解码器块(20)从比特流中提取适当的数据,并加载输入缓冲器(24)或可选的外部缓冲器(26)。 音频解码器块(28)从输入缓冲器(24)检索数据,并生成比例因子索引,存储在运算单元缓冲器(30)中的每码字值比特和子带样本。 硬件滤波器运算单元块(32)从算术单元缓冲器(30)检索信息,对数据进行去量化,变换和滤波,以产生加载到PCM缓冲器(34)中的PCM输出数据。 PCM缓冲器(34)内的数据由PCM输出块(36)输出到数 - 模转换器(16)。
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公开(公告)号:US5644310A
公开(公告)日:1997-07-01
申请号:US475251
申请日:1995-06-07
申请人: Frank L. Laczko, Sr. , Gerard Benbassat , Kenneth R. Cyr , Stephen H. Li , Shiu Wai Kam , Karen L. Walker , Jonathan L. Rowlands
发明人: Frank L. Laczko, Sr. , Gerard Benbassat , Kenneth R. Cyr , Stephen H. Li , Shiu Wai Kam , Karen L. Walker , Jonathan L. Rowlands
摘要: A data processing system (10) is disclosed which comprises a microprocessor host (12) coupled to a decoding system (14). A host interface block (18) receives a bit stream and passes bit stream on to a system decoder block (20). The system decoder block (20) extracts the appropriate data from the bit stream and loads an input buffer (24) or an optional external buffer (26). An audio decoder block (28) retrieves the data from the input buffer (24) and generates scale factor indices, bit per code word values and subband samples which are stored in an arithmetic unit buffer (30). A hardware filter arithmetic unit block (32) retrieves the information from the arithmetic unit buffer (30) and dequantizes, transforms and filters the data to generate PCM output data which is loaded into a PCM buffer (34). The data within the PCM buffer (34) is output by a PCM output block (36) to a digital-to-analog converter (16).
摘要翻译: 公开了一种数据处理系统(10),其包括耦合到解码系统(14)的微处理器主机(12)。 主机接口块(18)接收比特流并将比特流传送到系统解码器块(20)。 系统解码器块(20)从比特流中提取适当的数据,并加载输入缓冲器(24)或可选的外部缓冲器(26)。 音频解码器块(28)从输入缓冲器(24)检索数据,并生成比例因子索引,存储在运算单元缓冲器(30)中的每码字值比特和子带样本。 硬件滤波器运算单元块(32)从算术单元缓冲器(30)检索信息,对数据进行去量化,变换和滤波,以产生加载到PCM缓冲器(34)中的PCM输出数据。 PCM缓冲器(34)内的数据由PCM输出块(36)输出到数 - 模转换器(16)。
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3.
公开(公告)号:US5657423A
公开(公告)日:1997-08-12
申请号:US54768
申请日:1993-04-26
申请人: Gerard Benbassat , Frank L. Laczko, Sr. , Stephen H. Li , Kenneth R. Cyr , Jonathan L. Rowlands
发明人: Gerard Benbassat , Frank L. Laczko, Sr. , Stephen H. Li , Kenneth R. Cyr , Jonathan L. Rowlands
摘要: A data processing system (10) uses a microprocessor host (12) coupled to a decoding system (14). A hardware filter arithmetic unit block (32) retrieves decoded information from the arithmetic unit buffer (30) and dequantizes, transforms and filters the data to generate PCM output data which is loaded into a PCM buffer (34). An address circuit forms several addresses from a single value to accesses multiple sources of data and coefficients simultaneously for use by the hardware filter arithmetic unit.
摘要翻译: 数据处理系统(10)使用耦合到解码系统(14)的微处理器主机(12)。 硬件滤波器运算单元块(32)从算术单元缓冲器(30)检索解码信息,对数据进行去量化,变换和滤波,以产生加载到PCM缓冲器(34)中的PCM输出数据。 地址电路从单个值形成多个地址以同时访问数据和系数的多个源,以供硬件滤波器运算单元使用。
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