High voltage to low voltage level shifter
    1.
    发明申请
    High voltage to low voltage level shifter 失效
    高电压至低电平电平转换器

    公开(公告)号:US20050040853A1

    公开(公告)日:2005-02-24

    申请号:US10920632

    申请日:2004-08-18

    IPC分类号: H03K19/0185 H03K19/0175

    CPC分类号: H03K19/018521

    摘要: A shifter circuit comprises, in one embodiment, an input voltage divider stage comprising multiple transistors arranged in a transistor stack defining a plurality of intermediate nodes. The transistor stack is connected between an input signal and ground and has at least one output. An inverting buffer stage is connected to a supply voltage and coupled to the input voltage divider's output. The inverting buffer stage is configured to provide an inverted output signal. Means are provided for stepping up the inverted output signal, receiving a stepped up output signal and providing a level-shifted output signal at a voltage level lower than that of the input signal.

    摘要翻译: 在一个实施例中,移位器电路包括输入分压器级,其包括布置在限定多个中间节点的晶体管堆叠中的多个晶体管。 晶体管堆叠连接在输入信号和地之间,并具有至少一个输出。 反相缓冲级连接到电源电压并耦合到输入分压器的输出。 反相缓冲级被配置为提供反相输出信号。 提供了用于加强反相输出信号,接收升压输出信号并提供电压电平低于输入信号电压电平的电平移位输出信号的装置。

    Low voltage to extra high voltage level shifter and related methods
    2.
    发明申请
    Low voltage to extra high voltage level shifter and related methods 失效
    低电压至超高压电平转换器及相关方法

    公开(公告)号:US20050040852A1

    公开(公告)日:2005-02-24

    申请号:US10920630

    申请日:2004-08-18

    IPC分类号: H03K19/0185 H03K19/0175

    CPC分类号: H03K19/018521

    摘要: Shifter circuits comprise a matched translation stack comprising at least first and second stacks each of which comprising multiple transistors. The matched translation stack is configured to provide a primary logic level shift between a voltage level away from which a shift is desired (VddL) and a voltage level to which the shift is desired (VddH). One or more high voltage buffer stages are provided, at least one of which being connected with and biased by the matched translation stack. At least one high voltage buffer stage comprises multiple transistors arranged in a transistor stack that is biased by the first stack of the matched translation stack, and is connected to receive an input supplied by the second stack of the matched translation stack. The high voltage buffer stage also comprises an inverter that drives an output stage which is also driven by a low voltage buffer stage.

    摘要翻译: 移位器电路包括匹配的翻译堆栈,其包括至少第一和第二堆叠,每个堆叠包括多个晶体管。 匹配的翻译堆栈被配置为提供远离所需移位的电压电平(VddL)和期望移位的电压电平(VddH)之间的主逻辑电平移位。 提供一个或多个高电压缓冲级,其中至少一个与匹配的翻译堆叠连接并由其匹配。 至少一个高电压缓冲器级包括布置在晶体管堆叠中的多个晶体管堆叠的晶体管,该晶体管堆叠由匹配的转换堆叠的第一堆叠偏置,并被连接以接收由匹配的翻译堆叠的第二堆叠提供的输入。 高电压缓冲器级还包括驱动也由低电压缓冲级驱动的输出级的反相器。

    Low voltage to high voltage level shifter and related methods
    4.
    发明申请
    Low voltage to high voltage level shifter and related methods 失效
    低电压至高电平电平转换器及相关方法

    公开(公告)号:US20050040854A1

    公开(公告)日:2005-02-24

    申请号:US10920639

    申请日:2004-08-18

    IPC分类号: H03K19/0185 H03K19/0175

    CPC分类号: H03K19/018521

    摘要: A shifter circuit comprises a high and low voltage buffer stages and an output buffer stage. The high voltage buffer stage comprises multiple transistors arranged in a transistor stack having a plurality of intermediate nodes connecting individual transistors along the stack. The transistor stack is connected between a voltage level being shifted to and an input voltage. An inverter of this stage comprises multiple inputs and an output. Inverter inputs are connected to a respective intermediate node of the transistor stack. The low voltage buffer stage has an input connected to the input voltage and an output, and is operably connected to the high voltage buffer stage. The low voltage buffer stage is connected between a voltage level being shifted away from and a lower voltage. The output buffer stage is driven by the outputs of the high voltage buffer stage inverter and the low voltage buffer stage.

    摘要翻译: 移位电路包括高低电压缓冲级和输出缓冲级。 高电压缓冲级包括布置在晶体管堆叠中的多个晶体管,其具有沿堆叠连接各个晶体管的多个中间节点。 晶体管堆叠被连接在被移位的电压电平和输入电压之间。 该级的逆变器包括多个输入和一个输出。 逆变器输入端连接到晶体管堆叠的相应中间节点。 低电压缓冲级具有连接到输入电压和输出的输入,并且可操作地连接到高电压缓冲级。 低电压缓冲级连接在远离电压和较低电压的电压电平之间。 输出缓冲级由高压缓冲级反相器和低电压缓冲级的输出驱动。