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公开(公告)号：US20100063558A9
公开(公告)日：2010-03-11
申请号：US11429513
申请日：2006-05-05
申请人： Kevin Covey , Kelly Locke , Shawn Bertagnole
发明人： Kevin Covey , Kelly Locke , Shawn Bertagnole
IPC分类号： A61N1/39
CPC分类号： A61N1/3968 , A61N1/046
摘要： The invention presents techniques for making the operation of an automated external defibrillator easier to understand for an operator. The automated external defibrillator includes defibrillation electrodes packaged in a sealed, easy-to-open pouch. Visual cues such as instructive pictures show the operator how to open the pouch, retrieve the defibrillation electrodes and correctly position the electrodes on a patient's chest.
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2.发明授权Structured logic design method using figures of merit and a flowchart methodology 失效使用品质因数和流程图方法的结构化逻辑设计方法
公开(公告)号：US5258919A
公开(公告)日：1993-11-02
申请号：US546376
申请日：1990-06-28
CPC分类号： H01L27/0207 , G06F17/5045
摘要： The present invention provides a structured integrated circuit design methodology. The methodology is based on describing a two-phase logic function using a high level behavioral description flow chart, properly sizing devices to be used in the circuit for speed and reducing trial and error in circuit layout implementation using novel chip planning techniques. The methodology begins with the definition of signal types based on the circuit function that creates a particular signal and the type of input signal that feeds the circuit function. A rigid set of rules is then established for use of the signal types. Next the technical specification of the two-phase logic function is defined and utilized to create a behavioral flow chart using defined symbols. An associated database of corresponding Boolean equations is then created that defines the parameters of the various elements of the flow chart. The Boolean equations are then converted to a logic diagram either by coded state assignment or by direct implementation. The resulting logic diagram is then analyzed for speed utilizing a Figures of Merit technique for establishing device sizes. The resulting circuit design may then be carried through to layout utilizing conventional computer aided design (CAD) tools.
摘要翻译： 本发明提供一种结构化的集成电路设计方法。 该方法基于描述使用高级行为描述流程图的两相逻辑功能，适当地调整在电路中用于速度的设备，并且使用新颖的芯片规划技术减少电路布局实现中的试错误。 该方法从基于产生特定信号的电路功能和馈送电路功能的输入信号的类型的信号类型的定义开始。 然后建立一组刚性的规则来使用信号类型。 接下来，定义并利用两相逻辑功能的技术规范来创建使用定义符号的行为流程图。 然后创建相应布尔方程的相关数据库，其定义流程图的各种元素的参数。 然后通过编码状态分配或通过直接实现将布尔方程转换为逻辑图。 然后使用优点技术来建立装置尺寸来分析所得逻辑图的速度。 所得到的电路设计然后可以通过传统的计算机辅助设计（CAD）工具进行布局。
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公开(公告)号：US20060142831A1
公开(公告)日：2006-06-29
申请号：US11024138
申请日：2004-12-28
申请人： Richard Nova , Kevin Covey
发明人： Richard Nova , Kevin Covey
IPC分类号： A61N1/04
CPC分类号： A61B5/0408 , A61B5/04286 , A61B2562/242 , A61N1/046
摘要： Methods and apparatus are provided for a limited use ECG electrode set. The electrode set includes a plurality of limited use electrodes capable of being affixed to a human patient so as to receive patient information from the patient such as ECG data. Cables are also affixed to each electrode, and each cable is capable of transmitting patient information therethrough. A connector is affixed to each cable, and the connector is likewise capable of transmitting patient information. A sealing wedge may be molded around each cable forming a seal therebetween. The electrode set may be disposed at least partially in a packaging interior region, and the packaging may be hermetically sealed. Further the packaging may be sealed around the sealing wedge in forming the hermetic seal. The limited use electrode set may be opened and deployed from its packaging in situations that call for receiving patient data such as ECG information.
摘要翻译： 为有限使用的ECG电极组提供了方法和装置。 电极组包括能够固定在人类患者身上的多个有限使用电极，从患者接收患者信息，例如ECG数据。 电缆也固定到每个电极，并且每根电缆能够通过其传送患者信息。 连接器固定到每个电缆，并且连接器同样能够传送患者信息。 可以围绕每个电缆模制密封楔，以在它们之间形成密封。 电极组可以至少部分地设置在包装内部区域中，并且包装可以被气密密封。 此外，在形成气密密封件时，包装可以围绕密封楔密封。 在需要接收诸如ECG信息的患者数据的情况下，有限使用电极组可以从其包装打开和展开。
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公开(公告)号：US5444646A
公开(公告)日：1995-08-22
申请号：US204750
申请日：1994-03-01
申请人： D. Kevin Covey
发明人： D. Kevin Covey
CPC分类号： G06F7/5338 , G06F7/5443 , G06F9/3877 , G06F2207/3876 , G06F7/4991 , G06F7/49921
摘要： A multiply/accumulate unit utilizes a fully static 32-bit arithmetic logic unit with two stage carry bypass. A four transistor carry chain places minimal loading on the chain.
摘要翻译： 乘法/累加单元利用具有两级进位旁路的完全静态32位算术逻辑单元。 四极晶体管携带链将链路上的负载降至最低。
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公开(公告)号：US5319588A
公开(公告)日：1994-06-07
申请号：US987617
申请日：1992-12-09
CPC分类号： G06F7/5338 , G06F7/5443 , G06F9/3877 , G06F2207/3876 , G06F7/4991 , G06F7/49921
摘要： An arithmetic unit for multiplying and accumulating signed binary data and indicating an occurrence of a signed arithmetic overflow includes a multiplier-accumulator and an overflow flag register. The multiplier-accumulator receives and selectively multiples and accumulates signed binary data, and provides output data representing the multiplied and accumulated data and a sign bit representing its polarity, i.e. positive or negative. The flag register provides two "sticky" flag bits for indicating whether a signed arithmetic overflow (positive or negative) of the multiplied and accumulated data has occurred. The flag bits are "sticky" in that once a flag has been set, it cannot be reset by another arithmetic overflow condition. Instead, it must be specifically reset. The sign bit is used to selectively set one of the two sticky flag bits to a true state to indicate the direction (positive or negative) of the first arithmetic overflow. The sticky flag bits have mutually exclusive true states in that once a flag bit has been set true, the other flag bit cannot be set true until both flag bits have been specifically reset.
摘要翻译： 用于乘法和累加有符号二进制数据并指示有符号算术溢出发生的算术单元包括乘法器累加器和溢出标志寄存器。 乘法器 - 累加器接收和选择性地倍数并累加有符号的二进制数据，并且提供表示乘法和累积数据的输出数据和表示其极性的符号位，即正或负。 标志寄存器提供两个“粘性”标志位，用于指示已经发生乘法和累加数据的带符号算术溢出（正或负）。 标志位是“粘性”，因为一旦设置了一个标志，它就不能被另一个算术溢出条件复位。 相反，它必须特别重置。 符号位用于选择性地将两个粘性标志位中的一个设置为真实状态，以指示第一个算术溢出的方向（正或负）。 粘标志位具有相互排除的真实状态，因为一旦标志位被设置为真，则在两个标志位被特别复位之前，另一个标志位不能被设置为真。
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公开(公告)号：US20060206152A1
公开(公告)日：2006-09-14
申请号：US11429513
申请日：2006-05-05
申请人： Kevin Covey , Kelly Locke , Shawn Bertagnole
发明人： Kevin Covey , Kelly Locke , Shawn Bertagnole
IPC分类号： A61N1/39
CPC分类号： A61N1/3968 , A61N1/046
摘要： The invention presents techniques for making the operation of an automated external defibrillator easier to understand for an operator. The automated external defibrillator includes defibrillation electrodes packaged in a sealed, easy-to-open pouch. Visual cues such as instructive pictures show the operator how to open the pouch, retrieve the defibrillation electrodes and correctly position the electrodes on a patient's chest.
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公开(公告)号：US20050277991A1
公开(公告)日：2005-12-15
申请号：US10865232
申请日：2004-06-10
申请人： Kevin Covey , Thomas McGrath , Joseph Sullivan , Larry Nygaard , Richard Nova
发明人： Kevin Covey , Thomas McGrath , Joseph Sullivan , Larry Nygaard , Richard Nova
CPC分类号： A61N1/0492 , A61N1/046 , A61N1/048 , A61N1/3931 , A61N2001/083
摘要： The invention presents an apparatus and techniques for determining whether a medical electrode, such as a defibrillation electrode coupled to an automated external defibrillator, is in a condition for replacement. The determination can be made as a function of one or more data. In one exemplary embodiment, the determination is a function of one or more measurements of an impedance of a hydrogel bridge in a test module. In another exemplary embodiment, the determination is a function of one or more environmental condition data from one or more environmental sensors.
摘要翻译： 本发明提供了一种用于确定诸如与自动外部除颤器耦合的除颤电极之类的医用电极是否处于替换状态的装置和技术。 该确定可以作为一个或多个数据的函数。 在一个示例性实施例中，确定是测试模块中水凝胶桥的阻抗的一个或多个测量的函数。 在另一个示例性实施例中，确定是来自一个或多个环境传感器的一个或多个环境条件数据的函数。
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公开(公告)号：US5218564A
公开(公告)日：1993-06-08
申请号：US712208
申请日：1991-06-07
CPC分类号： G06F7/5338 , G06F7/5443 , G06F9/3877 , G06F2207/3876 , G06F7/4991 , G06F7/49921
摘要： An integrated circuit processor architecture that implements digital signal processing (DSP) functions with less hardware, improved speed and a more efficient layout. The central processing unit (CPU) resources are used in conjunction with an integrated multiply/accumulate unit to perform DSP operations. Use of the CPU's internal register for the circular buffer of the DSP multiply/accumulate function allows a minimum amount of lower speed hardware to be used for the multiply/accumulate unit and permits DSP operations to be performed in parallel. The multiply/accumulate unit takes advantage of the inherent accumulating properties of conventional multiplier designs to perform multiplication of two signed binary numbers using the modified Booth's algorithm but in both reduced cycle time and hardware requirements. This is accomplished by using the adder within the multiplier to sum the product terms. Instead of clearing the adder of the result of one multiplication before beginning another, the result is maintained and all subsequent partial products are added to it to generate a final output. The placement of the 32-bits of the multiply/accumulate unit's multiplicand register is arranged in two rows of 8 even bits and two rows of 8 odd bits to allow left shift by two with a single loop around and to provide direct interface with the 16-bit data latch register on its input and the rest of the 32-bit arithmetic logic unit (ALU) on its output.
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公开(公告)号：US5473554A
公开(公告)日：1995-12-05
申请号：US190253
申请日：1994-02-01
申请人： D. Kevin Covey
发明人： D. Kevin Covey
CPC分类号： G06F7/5338 , G06F7/5443 , G06F9/3877 , G06F2207/3876 , G06F7/4991 , G06F7/49921
摘要： A multiplexor has two data inputs and three control inputs. The multiplexor is realized using two stages of three-state inverters coupled by a logic gate so as to provide a compact layout and high speed drive capability.
摘要翻译： 多路复用器有两个数据输入和三个控制输入。 多路复用器通过逻辑门耦合的两级三态反相器实现，从而提供紧凑的布局和高速驱动能力。
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公开(公告)号：US5311458A
公开(公告)日：1994-05-10
申请号：US975399
申请日：1992-11-10
CPC分类号： G06F7/5338 , G06F7/5443 , G06F9/3877 , G06F2207/3876 , G06F7/4991 , G06F7/49921
摘要： An integrated circuit (IC) processor architecture is disclosed that implements hardware, signal processing (DSP) functions with less digital improved speed and a more efficient layout. The resources of the central processing unit (CPU) are used in conjunction with an integrated multiply/accumulate unit to perform DSP operations. Internal registers of the CPU are used to store pointers which reference a circular sample buffer. The CPU thus manages the selection and transfer of coefficients from the sample buffer to the multiply/accumulate unit, thereby allowing a minimum amount of lower speed hardware to be used for the multiply/accumulate unit and permitting DSP operations to be performed in parallel with CPU operations.
摘要翻译： 公开了一种集成电路（IC）处理器架构，其实现具有较少的数字改进速度和更有效的布局的硬件，信号处理（DSP）功能。 中央处理单元（CPU）的资源与集成乘法/累加单元结合使用以执行DSP操作。 CPU的内部寄存器用于存储引用循环采样缓冲区的指针。 CPU因此管理从采样缓冲器到乘法/累加单元的系数的选择和传送，从而允许将最低数量的较低速度的硬件用于乘法/累加单元，并允许与CPU并行执行DSP操作 操作。
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