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公开(公告)号：US5319588A
公开(公告)日：1994-06-07
申请号：US987617
申请日：1992-12-09
CPC分类号： G06F7/5338 , G06F7/5443 , G06F9/3877 , G06F2207/3876 , G06F7/4991 , G06F7/49921
摘要： An arithmetic unit for multiplying and accumulating signed binary data and indicating an occurrence of a signed arithmetic overflow includes a multiplier-accumulator and an overflow flag register. The multiplier-accumulator receives and selectively multiples and accumulates signed binary data, and provides output data representing the multiplied and accumulated data and a sign bit representing its polarity, i.e. positive or negative. The flag register provides two "sticky" flag bits for indicating whether a signed arithmetic overflow (positive or negative) of the multiplied and accumulated data has occurred. The flag bits are "sticky" in that once a flag has been set, it cannot be reset by another arithmetic overflow condition. Instead, it must be specifically reset. The sign bit is used to selectively set one of the two sticky flag bits to a true state to indicate the direction (positive or negative) of the first arithmetic overflow. The sticky flag bits have mutually exclusive true states in that once a flag bit has been set true, the other flag bit cannot be set true until both flag bits have been specifically reset.
摘要翻译： 用于乘法和累加有符号二进制数据并指示有符号算术溢出发生的算术单元包括乘法器累加器和溢出标志寄存器。 乘法器 - 累加器接收和选择性地倍数并累加有符号的二进制数据，并且提供表示乘法和累积数据的输出数据和表示其极性的符号位，即正或负。 标志寄存器提供两个“粘性”标志位，用于指示已经发生乘法和累加数据的带符号算术溢出（正或负）。 标志位是“粘性”，因为一旦设置了一个标志，它就不能被另一个算术溢出条件复位。 相反，它必须特别重置。 符号位用于选择性地将两个粘性标志位中的一个设置为真实状态，以指示第一个算术溢出的方向（正或负）。 粘标志位具有相互排除的真实状态，因为一旦标志位被设置为真，则在两个标志位被特别复位之前，另一个标志位不能被设置为真。
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公开(公告)号：US5218564A
公开(公告)日：1993-06-08
申请号：US712208
申请日：1991-06-07
CPC分类号： G06F7/5338 , G06F7/5443 , G06F9/3877 , G06F2207/3876 , G06F7/4991 , G06F7/49921
摘要： An integrated circuit processor architecture that implements digital signal processing (DSP) functions with less hardware, improved speed and a more efficient layout. The central processing unit (CPU) resources are used in conjunction with an integrated multiply/accumulate unit to perform DSP operations. Use of the CPU's internal register for the circular buffer of the DSP multiply/accumulate function allows a minimum amount of lower speed hardware to be used for the multiply/accumulate unit and permits DSP operations to be performed in parallel. The multiply/accumulate unit takes advantage of the inherent accumulating properties of conventional multiplier designs to perform multiplication of two signed binary numbers using the modified Booth's algorithm but in both reduced cycle time and hardware requirements. This is accomplished by using the adder within the multiplier to sum the product terms. Instead of clearing the adder of the result of one multiplication before beginning another, the result is maintained and all subsequent partial products are added to it to generate a final output. The placement of the 32-bits of the multiply/accumulate unit's multiplicand register is arranged in two rows of 8 even bits and two rows of 8 odd bits to allow left shift by two with a single loop around and to provide direct interface with the 16-bit data latch register on its input and the rest of the 32-bit arithmetic logic unit (ALU) on its output.
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公开(公告)号：US5311458A
公开(公告)日：1994-05-10
申请号：US975399
申请日：1992-11-10
CPC分类号： G06F7/5338 , G06F7/5443 , G06F9/3877 , G06F2207/3876 , G06F7/4991 , G06F7/49921
摘要： An integrated circuit (IC) processor architecture is disclosed that implements hardware, signal processing (DSP) functions with less digital improved speed and a more efficient layout. The resources of the central processing unit (CPU) are used in conjunction with an integrated multiply/accumulate unit to perform DSP operations. Internal registers of the CPU are used to store pointers which reference a circular sample buffer. The CPU thus manages the selection and transfer of coefficients from the sample buffer to the multiply/accumulate unit, thereby allowing a minimum amount of lower speed hardware to be used for the multiply/accumulate unit and permitting DSP operations to be performed in parallel with CPU operations.
摘要翻译： 公开了一种集成电路（IC）处理器架构，其实现具有较少的数字改进速度和更有效的布局的硬件，信号处理（DSP）功能。 中央处理单元（CPU）的资源与集成乘法/累加单元结合使用以执行DSP操作。 CPU的内部寄存器用于存储引用循环采样缓冲区的指针。 CPU因此管理从采样缓冲器到乘法/累加单元的系数的选择和传送，从而允许将最低数量的较低速度的硬件用于乘法/累加单元，并允许与CPU并行执行DSP操作 操作。
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公开(公告)号：US06735689B1
公开(公告)日：2004-05-11
申请号：US09562061
申请日：2000-05-01
IPC分类号： G06F932
CPC分类号： G06F9/30058 , G06F9/3017 , G06F9/322
摘要： Penalty for taking branch in pipelined processor is reduced by pre-calculating target of conditional branch before branch is encountered, thereby effectively converting branches to jumps. During program execution, pipeline penalty is reduced effectively to that of unconditional jump. Offset bits are replaced in a conditional branch with index bits based on addition of offset bits and a program counter value. Scheme reduces need for cycle to calculate target of taken branch. Scheme may be applied during cache fill or dead cycle when taken branch is read from pipelined cache.
摘要翻译： 在流水线处理器中采取分支的处罚方式是通过在分支之前预先计算条件分支的目标，从而有效地将分支转换为跳转。 在程序执行过程中，管道损失有效地降低到无条件跳转。 偏移位在带有索引位的条件分支中被替换，该偏移位基于偏移位的加法和程序计数器值。 方案减少了循环的需求，以计算采取分支的目标。 当从流水线缓存读取分支时，可以在缓存填充或死循环期间应用方案。
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公开(公告)号：US5600782A
公开(公告)日：1997-02-04
申请号：US321351
申请日：1994-10-11
申请人： Thomas W. S. Thomson
发明人： Thomas W. S. Thomson
IPC分类号： H04L12/413 , H04L29/06 , G06F11/00
CPC分类号： H04L12/40013 , H04L29/06 , H04L49/90 , H04L49/9068 , H04L2012/40215 , H04L2012/40273
摘要： A CAN node having an enhanced fault recovery system is disclosed. The CAN node includes a CAN protocol controller device which reconnects to a CAN bus from the node's busoff state only after the node has successfully decoded 128 good messages from other devices on the CAN bus. Such a system advantageously provides a CAN node which exits its busoff state with a high degree of confidence that the fault that caused the node to enter the busoff state has been cleared. The protocol controller device uses the eleven recessive bits that start at the acknowledgement delimiter and finish at the end of the third bit of intermission to recognize that a single message has been successfully decoded.
摘要翻译： 公开了具有增强故障恢复系统的CAN节点。 CAN节点包括一个CAN协议控制器设备，只有在节点成功解码了来自CAN总线上其他设备的128条好消息之后，才能从节点的总线状态重新连接到CAN总线。 这样的系统有利地提供了以高置信度退出其总线关闭状态的CAN节点，导致节点进入总线断开状态的故障已经被清除。 协议控制器设备使用从确认定界符开始的十一个隐性位，并在第三位中断结束时完成，以识别单个消息已被成功解码。
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公开(公告)号：US5442579A
公开(公告)日：1995-08-15
申请号：US345533
申请日：1994-11-28
申请人： Thomas W. S. Thomson
发明人： Thomas W. S. Thomson
CPC分类号： G06F7/5338 , G06F7/5443 , G06F9/3877 , G06F2207/3876 , G06F7/4991 , G06F7/49921
摘要： A method for summing a sequence of binary product terms utilizing a modified Booth's algorithm in an arithmetic unit, wherein the arithmetic unit has a multiplicand register, a multiplier register, a data bus coupled to the multiplicand register and to the multiplier register, a pad bit located adjacent to the least signficant bit of the multiplier register, and an adder register coupled to the multiplicand register. After initializing the adder register, the values of the pad bit and the two least significant bits of the multiplier register are examined and a modified Booth's algorithm is performed on the data in the multiplicand register based on the examined values. The multiplier value is then shifted 2 places to the right, through the pad bit, and the multiplicand value is shifted 2 places to the left. The values of the pad bit and the two least significant bits of the multiplier register are again examined and a modified Booth's algorithm is performed on the data in the multiplicand register based on the shifted examined values.
摘要翻译： 一种用于在算术单元中利用修正的布斯算法对二进制产品项序列求和的方法，其中所述算术单元具有被乘数寄存器，乘法器寄存器，耦合到被乘数寄存器和乘法器寄存器的数据总线， 位于乘法器寄存器的最小有效位附近，以及耦合到被乘数寄存器的加法器寄存器。 在初始化加法器寄存器之后，检查乘法器寄存器的pad位和两个最低有效位的值，并根据检查值对被乘数寄存器中的数据执行修改的Booth算法。 然后乘法器值通过pad位向右移位2个位置，并将乘法器值向左移位2个位置。 再次检查乘法器寄存器的焊盘位和两个最低有效位的值，并根据移位的检查值对被乘数寄存器中的数据执行修改后的布斯算法。
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