公开(公告)号：US20060166442A1

公开(公告)日：2006-07-27

申请号：US11338269

申请日：2006-01-24

申请人： Hae-Wang Lee ,  Key-Min Lee ,  Tae-Soo Park

发明人： Hae-Wang Lee ,  Key-Min Lee ,  Tae-Soo Park

IPC分类号： H01L21/336

CPC分类号： H01L21/823437 ,  H01L21/823412 ,  H01L29/66621 ,  H01L29/7833 ,  H01L29/7834

摘要： In a method for manufacturing a semiconductor device, a mask layer is formed on a semiconductor substrate. The mask layer and the substrate are patterned to form a device isolation layer defining an active region. The mask layer and the substrate are patterned in the active region to form a trench. A gate oxide layer is formed on the substrate at inner surfaces of the trench. The trench including the gate oxide layer is filled with a conductive layer for forming a gate electrode. The mask layer is then removed. Misalignment between the gate electrode and the substrate is thereby prevented. The gate electrode is made of polysilicon. By performing an ion implanting process, a conductivity type of the gate electrode is determined to provide a semiconductor device of a desired conductivity type.

摘要翻译： 在半导体器件的制造方法中，在半导体衬底上形成掩模层。 掩模层和衬底被图案化以形成限定有源区的器件隔离层。 在有源区中图案化掩模层和衬底以形成沟槽。 在沟槽的内表面上的衬底上形成栅氧化层。 包括栅极氧化物层的沟槽填充有用于形成栅电极的导电层。 然后去除掩模层。 由此防止了栅电极和基板之间的对准。 栅电极由多晶硅制成。 通过进行离子注入工艺，确定栅电极的导电类型以提供所需导电类型的半导体器件。

公开(公告)号：US06730572B2

公开(公告)日：2004-05-04

申请号：US10347230

申请日：2003-01-21

申请人： Key-Min Lee ,  Jae-Gyung Ahn

发明人： Key-Min Lee ,  Jae-Gyung Ahn

IPC分类号： H01L21331

CPC分类号： H01L21/823842 ,  H01L21/28052 ,  H01L21/823835

摘要： A method of forming silicide, especially in a CMOS device in which polysilicon grains in a p-type gate are re-doped with n-type impurities such as As and the like at a critical implantation dose. This increases the grain size of the polysilicon, which also reduces sheet resistance by securing thermal stability in subsequent process steps thereof. The present invention generally includes forming an undoped polysilicon layer, doping the polysilicon layer with p-type impurity ions, doping the p-doped polysilicon layer with ions that increase the grain size of the polysilicon layer by being heated, forming a metal layer on the twice-doped polysilicon layer, and forming a silicide layer by reacting a portion of the twice-doped polysilicon layer with the metal layer.

摘要翻译： 一种形成硅化物的方法，特别是在其中p型栅极中的多晶硅晶粒以临界注入剂量重新掺杂诸如As等的n型杂质的CMOS器件中。 这增加了多晶硅的晶粒尺寸，这也通过在其随后的工艺步骤中确保热稳定性而降低了薄层电阻。 本发明通常包括形成未掺杂的多晶硅层，用p型杂质离子掺杂多晶硅层，用掺杂p掺杂多晶硅层的离子掺杂，所述离子通过加热而增加多晶硅层的晶粒尺寸，在 双掺杂多晶硅层，并且通过使二掺杂多晶硅层的一部分与金属层反应而形成硅化物层。

公开(公告)号：US06528381B2

公开(公告)日：2003-03-04

申请号：US09770449

申请日：2001-01-29

申请人： Key-Min Lee ,  Jae-Gyung Ahn

发明人： Key-Min Lee ,  Jae-Gyung Ahn

IPC分类号： H01L21331

CPC分类号： H01L21/823842 ,  H01L21/28052 ,  H01L21/823835

摘要： A method of forming silicide, especially in a CMOS device in which polysilicon grains in a p-type gate are re-doped with n-type impurities such as As and the like at a critical implantation dose. This increases the grain size of the polysilicon, which also reduces sheet resistance by securing thermal stability in subsequent process steps thereof. The present invention generally includes forming an undoped polysilicon layer, doping the polysilicon layer with p-type impurity ions, doping the p-doped polysilicon layer with ions that increase the grain size of the polysilicon layer by being heated, forming a metal layer on the twice-doped polysilicon layer, and forming a silicide layer by reacting a portion of the twice-doped polysilicon layer with the metal layer.