公开(公告)号：US5157739A

公开(公告)日：1992-10-20

申请号：US726169

申请日：1991-07-02

申请人： Yasuo Masaki ,  Kimitoshi Hori ,  Hiroshi Uchino

发明人： Yasuo Masaki ,  Kimitoshi Hori ,  Hiroshi Uchino

IPC分类号： G06T1/20

CPC分类号： G06T1/20

摘要： An image input circuit, an image memory, an image processing circuit and an image output circuit are controlled by a host CPU through a host CPU bus and are connected by an image data bus so as to enable data transfer between each other. The image memory, image processing circuit and the image data bus for multiple-valued image and those for binary image are prepared. Consequently, storing, processing and transfer of multiple-valued image data and those for binary image data can be carried out independently from each other.

摘要翻译： 图像输入电路，图像存储器，图像处理电路和图像输出电路由主机CPU通过主机CPU总线进行控制，并通过图像数据总线进行连接，以实现彼此之间的数据传输。 准备了图像存储器，图像处理电路和用于多值图像的图像数据总线以及用于二值图像的图像数据总线。 因此，可以彼此独立地执行多值图像数据和二值图像数据的存储，处理和传送。

公开(公告)号：US5022090A

公开(公告)日：1991-06-04

申请号：US249643

申请日：1988-09-26

申请人： Yasuo Masaki ,  Kimitoshi Hori

发明人： Yasuo Masaki ,  Kimitoshi Hori

IPC分类号： G06T1/20 ,  G06T1/60

CPC分类号： G06T1/60

摘要： Each of the processing circuits connected to an image data bus is adapted such that a delay of n transfer clocks (n is a positive integer) or an integer multiple thereof is generated between the input and output data. Therefore, the delay time of the whole processing circuit becomes an integer multiple of a fixed time period, no matter what pipeline structure is adopted to connect the processing circuits. An address counter connected to the image memory through an address bus delays one read address by a plurality of cascade connected delay circuits and outputs the same as write address with the output of respective delay circuit switched successively, so that it seemingly operates in the same manner as in the case where there are a number of write address counters.

摘要翻译： 连接到图像数据总线的每个处理电路适于在输入和输出数据之间产生n个传送时钟（n为正整数）或其整数倍的延迟。 因此，无论采用哪种管道结构连接处理电路，整个处理电路的延迟时间都是固定时间段的整数倍。 通过地址总线连接到图像存储器的地址计数器通过多个级联连接的延迟电路延迟一个读取地址，并输出与写入地址相同的顺序连续切换的各个延迟电路的输出，使得其似乎以相同的方式工作 与存在多个写地址计数器的情况一样。

公开(公告)号：US5333263A

公开(公告)日：1994-07-26

申请号：US985760

申请日：1992-12-04

申请人： Yasuo Masaki ,  Kimitoshi Hori

发明人： Yasuo Masaki ,  Kimitoshi Hori

IPC分类号： G06F7/544 ,  G06F3/147

CPC分类号： G06F7/5443

摘要： A processing circuit comprising a multiplying circuit, an ALU, a bit shift circuit, LUT, selectors, and constant registers can be adapted to various data processing as a whole processing circuit by appropriately changing the operation states of respective circuits and changing the setting of constant values. By combining a plurality of processing circuits, a data processing circuit capable of larger number of functions can be realized.

摘要翻译： 包括乘法电路，ALU，位移电路，LUT，选择器和常数寄存器的处理电路可以通过适当地改变各个电路的工作状态并改变常数的设定，将其适用于作为整体处理电路的各种数据处理 价值观。 通过组合多个处理电路，可以实现能够实现更大数量的功能的数据处理电路。

公开(公告)号：US5576836A

公开(公告)日：1996-11-19

申请号：US331285

申请日：1994-10-28

申请人： Homare Sano ,  Katsumi Miwa ,  Norimasa Kubota ,  Kimitoshi Hori

发明人： Homare Sano ,  Katsumi Miwa ,  Norimasa Kubota ,  Kimitoshi Hori

IPC分类号： B65H31/00 ,  G03B27/46 ,  G03D13/00 ,  G03D15/00 ,  H04N1/00 ,  H04N1/387 ,  H04N1/21 ,  G03B27/52 ,  H04N1/46

CPC分类号： H04N1/00633 ,  G03B27/462 ,  G03D15/005 ,  H04N1/00567 ,  H04N1/3873 ,  G03B2227/005

摘要： A multi-picture image printing system includes a reception portion for receiving a plurality of recording mediums sequentially, each recording medium carrying a plurality of pictures; a multi-picture image generator operable to read the plurality of pictures recorded on each recording medium and generate a multi-picture image based on the read plurality of pictures; a printer operable to print the generated multi-picture image on a sheet; a medium discharger operable to discharge recording mediums; a sheet discharger operable to discharge printed sheets; a storing unit including a plurality of containers for containing discharged recording medium and printed sheet; and a controllers operable to control the medium discharger, sheet discharger, and the storing unit to place a recording medium and a printed sheet bearing a multi-picture image having pictures recorded on the recording medium in the same container.

摘要翻译： 多画面图像打印系统包括：接收部分，用于顺序地接收多个记录介质，每个记录介质承载多个图像; 多画面图像生成器，其可操作用于读取记录在每个记录介质上的多个图像，并且基于所读取的多个图像生成多图像图像; 打印机，用于将生成的多图像图像打印在纸张上; 介质放电器，其可操作以放出记录介质; 片材排出器，其可操作以排出印刷的片材; 存储单元，包括用于容纳排出的记录介质和印刷纸的多个容器; 以及控制器，其可操作以控制介质排出器，片材排出器和存储单元，以将记录介质和承载具有记录在记录介质上的图像的多图像图像的印刷片放置在同一容器中。

公开(公告)号：US5230042A

公开(公告)日：1993-07-20

申请号：US609025

申请日：1990-11-01

申请人： Yasuo Masaki ,  Kimitoshi Hori

发明人： Yasuo Masaki ,  Kimitoshi Hori

IPC分类号： G06F9/26 ,  G06F9/38

CPC分类号： G06F9/3877 ,  G06F9/265

摘要： A control circuit controls a hardware portion based on a microprogram set by a host CPU. Microinstructions constituting the microprogram comprise an instruction for setting an initial value of an address counter for reading microprogram as well as an instruction for controlling the hardware portion. The initial value setting instruction comprises an initial value setting instruction which uses the state of a flag register, which is set dependent on a change of state generated from the arithmetic processing in the hardware portion, as a condition. Therefore, the flow of reading of the microprogram can be changed corresponding to the change of the state generated by the arithmetic processing in the hardware portion.

摘要翻译： 控制电路根据由主机CPU设置的微程序控制硬件部分。 构成微程序的微指令包括用于设置用于读取微程序的地址计数器的初始值的指令以及用于控制硬件部分的指令。 初始值设定指令包括使用根据硬件部分的运算处理生成的状态变化而设定的标志寄存器的状态作为条件的初始值设定指示。 因此，可以根据由硬件部分中的运算处理产生的状态的变化来改变微程序的读取流程。

公开(公告)号：US4912680A

公开(公告)日：1990-03-27

申请号：US239749

申请日：1988-09-02

申请人： Yasuo Masaki ,  Kimitoshi Hori

发明人： Yasuo Masaki ,  Kimitoshi Hori

IPC分类号： G11C7/10

CPC分类号： G11C7/1075

摘要： A plurality of registers for writing are connected to data input portions of respective memory devices and a plurality of registers for reading are connected to the data output portions thereof. A random access bus and a serial access bus are respectively connected to both of the registers for writing and the registers for reading. A control circuit controls the memory devices, registers for writing and the registers for reading to effect serial input/output control and random access control.

摘要翻译： 用于写入的多个寄存器连接到各个存储器件的数据输入部分，并且用于读取的多个寄存器连接到其数据输出部分。 随机存取总线和串行存取总线分别连接到两个用于写入的寄存器和用于读取的寄存器。 控制电路控制存储器件，用于写入的寄存器和用于读取的寄存器以实现串行输入/输出控制和随机存取控制。