公开(公告)号：US08780171B2

公开(公告)日：2014-07-15

申请号：US12970302

申请日：2010-12-16

申请人： Koji Kamiya ,  Mayuki Hashi ,  Kinichi Ootsu

发明人： Koji Kamiya ,  Mayuki Hashi ,  Kinichi Ootsu

IPC分类号： H04N13/00

CPC分类号： H04N13/178 ,  H04N13/139 ,  H04N13/161 ,  H04N13/194 ,  H04N13/239

摘要： Disclosed herein is a video signal processor including: a combining process section adapted to superimpose a first marker signal on a first video signal component at a specific position and superimpose a second marker signal on a second video signal component at roughly the same position as the specific position; and a control section adapted to control the condition of superimposition of the first and second marker signals so that an image appears to indicate that the first and second marker signals are combined correctly when the first and second video signal components are combined in a correct phase relationship, and so that an image appears to indicate that the first and second marker signals are combined incorrectly if the first and second video signal components are combined in an incorrect phase relationship.

摘要翻译： 本文公开了一种视频信号处理器，包括：组合处理部分，适于将第一标记信号叠加在特定位置的第一视频信号分量上，并将第二标记信号叠加在与特定的位置大致相同位置的第二视频信号分量上 位置; 以及控制部分，适于控制第一和第二标记信号的叠加条件，使得当第一和第二视频信号分量以正确的相位关系组合时，图像看起来表明第一和第二标记信号被正确组合 并且使得如果第一和第二视频信号分量以不正确的相位关系组合，则图像看起来表明第一和第二标记信号被不正确地组合。

公开(公告)号：US08558905B2

公开(公告)日：2013-10-15

申请号：US13079422

申请日：2011-04-04

申请人： Kinichi Ootsu ,  Yasunobu Kojima

发明人： Kinichi Ootsu ,  Yasunobu Kojima

IPC分类号： H04N5/232

CPC分类号： H04N5/23203

摘要： A transmission device includes: a transceiving unit transceiving a serial signal generated by serially converting data based on a clock signal of a frequency selected from frequencies used as clock components of the serial signal and including the clock signal of the selected frequency; a clock recovering unit receiving the serial signal received by the transceiving unit and recovers a recovered clock signal from the serial signal; a match determination unit receiving the recovered clock signal and determines whether a frequency of the recovered clock signal matches each of the frequencies; and a frequency controller performing, if the match determination unit determines that the frequency of the recovered clock signal matches each of the frequencies, a control to determine the frequency of the recovered clock signal as the matching frequency, wherein the frequency of the recovered clock signal is switched between the frequencies until the frequency is determined by the frequency controller.

摘要翻译： 传输装置包括：收发单元，收发通过串行转换数据产生的串行信号，所述串行信号基于从用作所述串行信号的时钟分量的频率中选出的频率的时钟信号，并包括所选频率的时钟信号; 时钟恢复单元，接收由收发单元接收的串行信号，并从串行信号中恢复恢复的时钟信号; 匹配确定单元，接收恢复的时钟信号，并确定恢复的时钟信号的频率是否与每个频率匹配; 以及频率控制器，如果所述匹配确定单元确定所述恢复的时钟信号的频率与每个所述频率匹配，则确定所述恢复的时钟信号的频率作为所述匹配频率的控制，其中所述恢复的时钟信号的频率 在频率之间切换，直到频率由频率控制器确定。

公开(公告)号：US20110249129A1

公开(公告)日：2011-10-13

申请号：US13079422

申请日：2011-04-04

申请人： Kinichi OOTSU ,  YASUNOBU KOJIMA

发明人： Kinichi OOTSU ,  YASUNOBU KOJIMA

IPC分类号： H04L7/04 ,  H04N5/225

CPC分类号： H04N5/23203

摘要： A transmission device includes: a transceiving unit transceiving a serial signal generated by serially converting data based on a clock signal of a frequency selected from frequencies used as clock components of the serial signal and including the clock signal of the selected frequency; a clock recovering unit receiving the serial signal received by the transceiving unit and recovers a recovered clock signal from the serial signal; a match determination unit receiving the recovered clock signal and determines whether a frequency of the recovered clock signal matches each of the frequencies; and a frequency controller performing, if the match determination unit determines that the frequency of the recovered clock signal matches each of the frequencies, a control to determine the frequency of the recovered clock signal as the matching frequency, wherein the frequency of the recovered clock signal is switched between the frequencies until the frequency is determined by the frequency controller.

摘要翻译： 传输装置包括：收发单元，收发通过串行转换数据产生的串行信号，所述串行信号基于从用作所述串行信号的时钟分量的频率中选出的频率的时钟信号，并包括所选频率的时钟信号; 时钟恢复单元，接收由收发单元接收的串行信号，并从串行信号中恢复恢复的时钟信号; 匹配确定单元，接收恢复的时钟信号，并确定恢复的时钟信号的频率是否与每个频率匹配; 以及频率控制器，如果所述匹配确定单元确定所述恢复的时钟信号的频率与每个所述频率匹配，则确定所述恢复的时钟信号的频率作为所述匹配频率的控制，其中所述恢复的时钟信号的频率 在频率之间切换，直到频率由频率控制器确定。

公开(公告)号：US20110149023A1

公开(公告)日：2011-06-23

申请号：US12970302

申请日：2010-12-16

申请人： Koji Kamiya ,  Mayuki Hashi ,  Kinichi Ootsu

发明人： Koji Kamiya ,  Mayuki Hashi ,  Kinichi Ootsu

IPC分类号： H04N13/00

CPC分类号： H04N13/178 ,  H04N13/139 ,  H04N13/161 ,  H04N13/194 ,  H04N13/239

摘要： Disclosed herein is a video signal processor including: a combining process section adapted to superimpose a first marker signal on a first video signal component at a specific position and superimpose a second marker signal on a second video signal component at roughly the same position as the specific position; and a control section adapted to control the condition of superimposition of the first and second marker signals so that an image appears to indicate that the first and second marker signals are combined correctly when the first and second video signal components are combined in a correct phase relationship, and so that an image appears to indicate that the first and second marker signals are combined incorrectly if the first and second video signal components are combined in an incorrect phase relationship.

摘要翻译： 本文公开了一种视频信号处理器，包括：组合处理部分，适于将第一标记信号叠加在特定位置的第一视频信号分量上，并将第二标记信号叠加在与特定的位置大致相同位置的第二视频信号分量上 位置; 以及控制部分，适于控制第一和第二标记信号的叠加条件，使得当第一和第二视频信号分量以正确的相位关系组合时，图像看起来表明第一和第二标记信号被正确组合 并且使得如果第一和第二视频信号分量以不正确的相位关系组合，则图像看起来表明第一和第二标记信号被不正确地组合。