公开(公告)号：US20090147449A1

公开(公告)日：2009-06-11

申请号：US12330027

申请日：2008-12-08

申请人： Keiko MATSUOKA ,  Shoji UMEDA ,  Yoshiyuki FUSHIMI ,  Koji TEZUKA

发明人： Keiko MATSUOKA ,  Shoji UMEDA ,  Yoshiyuki FUSHIMI ,  Koji TEZUKA

IPC分类号： H01G9/025

CPC分类号： H01G9/012 ,  H01G9/10 ,  H01G9/14 ,  H01G9/15 ,  Y10T29/417 ,  Y10T29/49121

摘要： A solid electrolytic capacitor includes a capacitor element, an anode lead frame, a cathode lead frame, and a mold resin portion. The anode lead frame includes an anode terminal portion and a rising portion, and the anode terminal portion is exposed at the bottom surface of the mold resin portion. The rising portion is formed integral with the anode terminal portion, and rises to the anode portion. In the rising portion, a through hole is formed. The cathode lead frame includes a cathode terminal portion, a pair of side surface portions and a step portion. Thus, a solid electrolytic capacitor allowing highly accurate and reliable attachment of the capacitor element to the lead frame without using any additional member is provided.

摘要翻译： 固体电解电容器包括电容器元件，阳极引线框架，阴极引线框架和模制树脂部分。 阳极引线框架包括阳极端子部分和上升部分，并且阳极端子部分在模制树脂部分的底表面处露出。 上升部分与阳极端子部分形成一体，并且上升到阳极部分。 在上升部分，形成通孔。 阴极引线框架包括阴极端子部分，一对侧表面部分和台阶部分。 因此，提供了一种固体电解电容器，其允许将电容器元件高度精确和可靠地附接到引线框架而不使用任何附加构件。

公开(公告)号：US5555542A

公开(公告)日：1996-09-10

申请号：US583962

申请日：1996-01-11

申请人： Takao Ogura ,  Shigeo Amemiya ,  Koji Tezuka ,  Takafumi Chujo

发明人： Takao Ogura ,  Shigeo Amemiya ,  Koji Tezuka ,  Takafumi Chujo

IPC分类号： H04L12/701 ,  H04L12/56

CPC分类号： H04L45/00

摘要： A packet directional path identifier transfer system contains on the transmission side thereof, a means 2 of converting packet directional path identifier data into bit map information in which an address of each bit corresponds to a packet directional path identifier. The system contains on the reception side thereof, a means 5 for inversely converting the bit map information of the packet directional path identifier data to the packet directional path identifier data. Otherwise, the system further contains on the transmission side thereof, means 8 and 10 for determining the top and bottom values of the packet directional path identifier data to be transmitted, and a means 9 for converting the packet directional path identifier data between the top and bottom values into bit map information, and at the reception side thereof, a means 13 for inversely converting into the initial packet directional path identifier data the bit map information of the packet directional path identifier between the top and bottom values. Further, the top value of the identifier(s) of the newly-set packet directional path(s) determined from the non-used packet directional path identifier(s) in the outgoing packet directional path of the transmission-side node and the number of the newly-set packet directional path identifier(s) are transmitted, and a reference is made to the incoming packet directional path identifier table at the reception-side node to recognize the newly-set packet directional path(s) based on the information received. (FIGS. 1 and 2.)

摘要翻译： 分组定向路径标识符传送系统在其发送侧包含将分组方向路径标识符数据转换为比特映射信息的装置2，其中每个比特的地址对应于分组方向路径标识符。 该系统在其接收侧包含用于将分组方向路径标识符数据的位图信息逆向转换为分组方向路径标识符数据的装置5。 否则，该系统在其发送侧还包含用于确定要发送的分组有向路径标识符数据的上限值和下限值的装置8和10，以及用于将分组方向路径标识符数据在顶部和 底部值作为位图信息，并且在其接收侧具有用于将初始分组方向路径标识符数据逆向转换为顶部和底部值之间的分组方向路径标识符的位图信息的装置13。 此外，根据发送侧节点的输出分组定向路径中的未使用的分组有向路径标识符确定的新设定的分组定向路径的标识符的顶值， 发送新设定的分组方向路径标识符，并且参考在接收侧节点处的输入分组定向路径标识符表，以基于该信息来识别新设置的分组定向路径 收到了 （图1和图2）。

公开(公告)号：US5539743A

公开(公告)日：1996-07-23

申请号：US700166

申请日：1991-05-17

申请人： Shigeo Amemiya ,  Hiroshi Takeo ,  Koji Tezuka ,  Kazuo Iguchi

发明人： Shigeo Amemiya ,  Hiroshi Takeo ,  Koji Tezuka ,  Kazuo Iguchi

IPC分类号： H04L12/403 ,  H04J3/02

CPC分类号： H04L12/403

摘要： In a multiple access system for a communication network in which a main station (M) is coupled to a plurality of sub stations (S1-Sn) via lines, each sub station (S1-Sn) comprises a data buffer (1) for storing data (DATA-TE) which is to be transmitted, and a request information forming part (2) for sending to the main station (M) transmission request information (REQ) which includes reservation information obtained based on a data quantity (IN) stored within the data buffer, and the main station (M) comprises a control part (5) for forming a time table (3) of a data transmission reservation time and a corresponding sub station number based on the reservation information included in the transmission request information from each sub station and for giving authority to transmit data to each sub station by transmitting a data transmission enable signal (TENO) to each sub station depending on the data transmission reservation time and the sub station number of the time table.

摘要翻译： PCT No.PCT / JP90 / 01183 Sec。 371日期1991年5月17日 102（e）日期1991年5月17日PCT 1990年9月17日PCT PCT。 公开号WO91 / 04623 日期：1991年04月4日，在通过线路将主站（M）与多个子站（S1-Sn）连接的通信网络的多址系统中，每个子站（S1-Sn）包括数据缓冲器 （1），用于存储要发送的数据（DATA-TE）以及用于向主站（M）发送包括根据数据获得的预约信息的发送请求信息（REQ）的请求信息形成部分（2） 数量（IN）存储在数据缓冲器中，主站（M）包括用于形成数据传输预约时间的时间表（3）的控制部分（5）和基于包括的预约信息的对应的子站号 在来自每个子站的发送请求信息中，并且通过根据数据传输预约时间和时间标签的子站号码向每个子站发送数据发送使能信号（TENO）来授权向每个子站发送数据 le。

公开(公告)号：US5166675A

公开(公告)日：1992-11-24

申请号：US726637

申请日：1991-07-02

申请人： Shigeo Amemiya ,  Koji Tezuka ,  Tomohiro Shinomiya ,  Hiroshi Takeo ,  Tetsuo Soejima ,  Kazuo Iguchi

发明人： Shigeo Amemiya ,  Koji Tezuka ,  Tomohiro Shinomiya ,  Hiroshi Takeo ,  Tetsuo Soejima ,  Kazuo Iguchi

IPC分类号： H04L12/403

CPC分类号： H04L12/40143 ,  H04L12/403

摘要： A communication system containing a master station and a plurality of slave stations. The master station receives a request from one of the plurality of slave stations and memorizes one or more requests from one or more slave stations. The master station also sends a request sending allowance signal which addresses one of the plurality of slave stations to give an allowance to send a request for sending data, and sends a data sending allowance signal which addresses one of the plurality of slave stations to give an allowance to send data, according to a request which is memorized. Each of the slave stations detects a request sending allowance signal which addresses its own slave station, and a data sending allowance signal which addresses its own slave station. Each of the slave stations also sends a request for sending data to the master station when its own slave station detects a request sending allowance signal which addresses its own slave station. In addition, each slave station sends data to the master station when its own slave station detects a data sending allowance signal which addresses its own slave station.

摘要翻译： 一种包含主站和多个从站的通信系统。 主站接收来自多个从站中的一个的请求，并存储来自一个或多个从站的一个或多个请求。 主站还发送请求发送允许信号，该请求发送允许信号寻址多个从站中的一个从站给发送请求发送数据的余地，并且发送寻址多个从站中的一个从站的数据发送允许信号，以给出 根据要记录的要求发送数据。 每个从站检测到寻址其自己的从站的请求发送允许信号，以及寻址其自己的从站的数据发送允许信号。 当其自己的从站检测到寻址其自己的从站的请求发送允许信号时，每个从站还发送向主站发送数据的请求。 另外，每个从站在其自己的从站检测到寻址其自己的从站的数据发送允许信号时，向主站发送数据。

公开(公告)号：US5086436A

公开(公告)日：1992-02-04

申请号：US529326

申请日：1990-05-29

申请人： Koji Tezuka ,  Shigeo Amemiya ,  Tomohiro Shinomiya ,  Kazuo Iguchi ,  Tetsuo Soejima

发明人： Koji Tezuka ,  Shigeo Amemiya ,  Tomohiro Shinomiya ,  Kazuo Iguchi ,  Tetsuo Soejima

IPC分类号： H04L25/38 ,  H03M7/30 ,  H04L7/04 ,  H04L25/49

CPC分类号： H04L25/491 ,  H03M7/30

摘要： A coded transmission system wherein each bit of transmitted data having a logical value is coded depending on a coded result of a preceding bit. The coded transmission system contains a sender-side apparatus, a transmission line, and a receiver-side apparatus. In the sender-side apparatus, a resetting bit and a message are generated; a code of a bit last transmitted which is necessary to code a bit which is to be transmitted next is memorized in a first preceding code memorizing circuit; and the content of the first preceding code memorizing circuit is reset to an initial code responding to the resetting bit. A coding circuit receives the resetting bit and the message, codes each bit of the message in accordance with a predetermined coding rule and the content of the first preceding code memorizing circuit, and codes the resetting bit to a predetermined resetting code which is different from the codes used in the coding of the message. In the receiver-side apparatus, a code of a bit last received which is necessary to decode a code of a bit which is received next is memorized in a second preceding code memorizing circuit. A resetting circuit resets a content of a second preceding code memorizing circuit to a predetermined initial code when receiving the resetting code. A decoding circuit decodes the received codes corresponding to the message in accordance with the predetermined coding rule and the content of the second preceding code memorizing circuit.

公开(公告)号：US09744443B2

公开(公告)日：2017-08-29

申请号：US14110608

申请日：2012-04-11

申请人： Koji Tezuka ,  Masaki Ota ,  Kentaro Honma

发明人： Koji Tezuka ,  Masaki Ota ,  Kentaro Honma

IPC分类号： A63F9/24 ,  A63F13/30 ,  G07F17/32

CPC分类号： A63F13/55 ,  A63F13/12 ,  A63F2300/201 ,  A63F2300/5586 ,  G07F17/3237

摘要： A server is connected to a terminal via a network, and manages registration of game information, the terminal performing a first game process that utilizes stored game information, and a second game process that utilizes registered game information. The server stores terminal identification information of the terminal and an allowable registration count of the terminal in a linked manner, updates the allowable registration count while being linked to the terminal identification information corresponding to a received update allowable registration count, transmits a registration permission notification to the terminal upon reception of a game information registration request from the terminal when the allowable registration count is equal to or larger than a given number, transmits a registration non-permission notification to the terminal when the allowable registration count is less than the given number, and decrements the allowable registration count when the server has transmitted the registration permission notification to the terminal.

公开(公告)号：US20110249375A1

公开(公告)日：2011-10-13

申请号：US13165197

申请日：2011-06-21

申请人： Keiko MATSUOKA ,  Shoji UMEDA ,  Yoshiyuki FUSHIMI ,  Koji TEZUKA

发明人： Keiko MATSUOKA ,  Shoji UMEDA ,  Yoshiyuki FUSHIMI ,  Koji TEZUKA

IPC分类号： H01G9/012 ,  H01G9/15 ,  H01R43/00 ,  H01G9/048

CPC分类号： H01G9/012 ,  H01G9/10 ,  H01G9/14 ,  H01G9/15 ,  Y10T29/417 ,  Y10T29/49121

摘要： A solid electrolytic capacitor includes a capacitor element, an anode lead frame, a cathode lead frame, and a mold resin portion. The anode lead frame includes an anode terminal portion and a rising portion, and the anode terminal portion is exposed at the bottom surface of the mold resin portion. The rising portion is formed integral with the anode terminal portion, and rises to the anode portion. In the rising portion, a through hole is formed. The cathode lead frame includes a cathode terminal portion, a pair of side surface portions and a step portion. Thus, a solid electrolytic capacitor allowing highly accurate and reliable attachment of the capacitor element to the lead frame without using any additional member is provided.

摘要翻译： 固体电解电容器包括电容器元件，阳极引线框架，阴极引线框架和模制树脂部分。 阳极引线框架包括阳极端子部分和上升部分，并且阳极端子部分在模制树脂部分的底表面处露出。 上升部分与阳极端子部分形成一体，并且上升到阳极部分。 在上升部分，形成通孔。 阴极引线框架包括阴极端子部分，一对侧表面部分和台阶部分。 因此，提供了一种固体电解电容器，其允许将电容器元件高度精确和可靠地附接到引线框架而不使用任何附加构件。

公开(公告)号：US20140113728A1

公开(公告)日：2014-04-24

申请号：US14110608

申请日：2012-04-11

申请人： Koji Tezuka ,  Masaki Ota ,  Kentaro Honma

发明人： Koji Tezuka ,  Masaki Ota ,  Kentaro Honma

IPC分类号： A63F13/30

CPC分类号： A63F13/55 ,  A63F13/12 ,  A63F2300/201 ,  A63F2300/5586 ,  G07F17/3237

摘要： A server is connected to a terminal via a network, and manages registration of game information, the terminal performing a first game process that utilizes stored game information, and a second game process that utilizes registered game information. The server stores terminal identification information of the terminal and an allowable registration count of the terminal in a linked manner, updates the allowable registration count while being linked to the terminal identification information corresponding to a received update allowable registration count, transmits a registration permission notification to the terminal upon reception of a game information registration request from the terminal when the allowable registration count is equal to or larger than a given number, transmits a registration non-permission notification to the terminal when the allowable registration count is less than the given number, and decrements the allowable registration count when the server has transmitted the registration permission notification to the terminal.

摘要翻译： 服务器通过网络连接到终端，并且管理游戏信息的登记，执行使用存储的游戏信息的第一游戏进程的终端和利用注册的游戏信息的第二游戏进程。 服务器以连接的方式存储终端的终端识别信息和终端的允许注册计数，在与所接收到的更新许可注册计数相对应的终端识别信息链接的同时更新允许注册计数，将注册许可通知发送到 当允许的登记计数等于或大于给定数量时从终端接收到游戏信息登记请求时的终端，当可允许登记数小于给定数量时向终端发送登记不许可通知， 并且当服务器向终端发送注册许可通知时，减少允许的注册计数。

公开(公告)号：US20070142976A1

公开(公告)日：2007-06-21

申请号：US11640573

申请日：2006-12-18

申请人： Koji Tezuka

发明人： Koji Tezuka

IPC分类号： G05D23/00

CPC分类号： G05D23/19

摘要： According to one embodiment, there is provided an electronic apparatus including: a main body configured to be used in a first mode and a second mode; a fan installed in the main body; a control section that controls the fan on the basis of a detected acceleration of the main body, the detected temperature inside of the main body, and the selected mode. The control section includes: a storage that stores a first setting for controlling the fan in a first temperature range and a second setting for controlling the fan in a second temperature range that includes a temperature range lower than the first temperature range; and a setting select section that selects one setting among the first and second setting.

摘要翻译： 根据一个实施例，提供一种电子设备，包括：主体，被配置为在第一模式和第二模式中使用; 安装在主体上的风扇; 控制部，其基于检测到的主体的加速度，主体内的检测温度和所选择的模式来控制风扇。 控制部包括：存储在第一温度范围内存储用于控制风扇的第一设定的第一设定和用于在包含低于第一温度范围的温度范围的第二温度范围内控制风扇的第二设定; 以及在第一和第二设置中选择一个设置的设置选择部分。

公开(公告)号：US5636206A

公开(公告)日：1997-06-03

申请号：US445397

申请日：1995-05-19

申请人： Shigeo Amemiya ,  Yuichi Matsuda ,  Takao Ogura ,  Yasuki Fujii ,  Koji Tezuka ,  Hiromi Ueda ,  Hitoshi Uematsu

发明人： Shigeo Amemiya ,  Yuichi Matsuda ,  Takao Ogura ,  Yasuki Fujii ,  Koji Tezuka ,  Hiromi Ueda ,  Hitoshi Uematsu

IPC分类号： H04Q3/00 ,  H04J3/14

CPC分类号： H04J3/14

摘要： An alarm masking system is provided which is capable of implementing alarm priority processing or alarm inhibit processing in ATM transmission equipment. In ATM transmission equipment, a received virtual path or virtual channel is switched by means of a switching unit and then sent to an interface unit. In doing this, if a higher priority alarm is detected or received at a reception side interface unit, an intra-office tag is added to the alarm cell and then it is output, so that by detecting this intra-office tag it is possible to inhibit generation of lower priority alarms in response to the higher order alarm.

摘要翻译： 提供一种能够在ATM传输设备中实现报警优先处理或报警禁止处理的报警屏蔽系统。 在ATM传输设备中，通过交换单元切换接收的虚拟路径或虚拟信道，然后发送到接口单元。 这样做时，如果在接收侧接口单元检测到或接收到较高优先级的报警，则向报警单元添加局内标签，然后输出，从而通过检测该室内标签， 响应高阶报警，禁止生成较低优先级的报警。