公开(公告)号：US5455936A

公开(公告)日：1995-10-03

申请号：US234566

申请日：1994-04-28

申请人： Kouji Maemura

发明人： Kouji Maemura

IPC分类号： G06F11/28 ,  G06F11/26 ,  G06F11/36 ,  G06F11/30

CPC分类号： G06F11/261 ,  G06F11/364 ,  G06F11/3648

摘要： A debugger for a microprocessor, includes an instruction substituting circuit for tracing a memory access performed by the microprocessor and for substituting a predetermined branch instruction for an instruction which is read out from a predetermined address by the microprocessor; A background monitor is configured to give the microprocessor a memory space which is separated from the user space and is unique to the debugger. After the predetermined branch instruction has been substituted and after a break acknowledge signal indicating that an execution of the predetermined branch instruction has been activated, the debugger executes a program stored in the background monitor, and supplies a cache clear signal to the cache clear terminal at the start and end of the program in the background monitor.

摘要翻译： 用于微处理器的调试器包括用于跟踪由微处理器执行的存储器访问的指令替换电路，并且用于将预定分支指令替换为由微处理器从预定地址读出的指令; 后台监视器被配置为给予微处理器与用户空间分离并且对调试器是唯一的存储器空间。 在预定分支指令已经被替换之后，并且在指示预定分支指令的执行已经被激活的中断确认信号之后，调试器执行存储在后台监视器中的程序，并且将缓存清除信号提供给高速缓存清除终端 程序的开始和结束在后台监视器中。

公开(公告)号：US5535350A

公开(公告)日：1996-07-09

申请号：US907920

申请日：1992-07-02

申请人： Kouji Maemura

发明人： Kouji Maemura

IPC分类号： G06F12/12 ,  B65H54/553 ,  G06F12/08 ,  G06F15/78 ,  G06F13/00

CPC分类号： G06F12/0859

摘要： A cache memory unit to be incorporated in a microprocessor reduces overhead caused by cache misses by processing all main memory replacement data at the same time as their registration or storage in the cache memory during a replacement access cycle. For this purpose, the cache memory unit includes a prefetch pointer to store the address for retrieval of cache memory, an address updater to update an internal address of the cache memory, and a cache control circuit to control the cache memory unit. When a cache miss occurs, the address causing the miss is stored in a replacement address register and, until the main memory replacement data is stored in the cache memory, the contents in the replacement address register are output to an internal address bus. On the other hand, the contents in the prefetch pointer are selectively updated.

摘要翻译： 要结合在微处理器中的高速缓冲存储器单元通过在更换访问周期期间与其在高速缓存存储器中的注册或存储同时处理所有主存储器替换数据来减少由高速缓存未命中引起的开销。 为此，高速缓冲存储器单元包括用于存储用于检索高速缓冲存储器的地址的预取指针，用于更新高速缓冲存储器的内部地址的地址更新器，以及用于控制高速缓冲存储器单元的高速缓存控制电路。 当发生高速缓存未命中时，导致未命中的地址被存储在替换地址寄存器中，并且直到主存储器替换数据存储在高速缓冲存储器中，替换地址寄存器中的内容被输出到内部地址总线。 另一方面，预取指针中的内容被有选择地更新。

公开(公告)号：US5247624A

公开(公告)日：1993-09-21

申请号：US491952

申请日：1990-03-12

申请人： Yasuhiko Koumoto ,  Kouji Maemura

发明人： Yasuhiko Koumoto ,  Kouji Maemura

IPC分类号： G06F9/26 ,  G06F9/315

CPC分类号： G06F9/30032 ,  G06F9/267 ,  G06F9/268

摘要： A microprogram controller advances the initiation of a string of microinstructions for certain macroinstructions to enhance the overall speed of instruction execution. The microprogram controller includes a memory (50) for storing microinstructions and a generator (30) for generating an initial microinstruction of a certain macroinstruction. A selector (60) selects one of a microinstruction read out of the memory and the initial microinstruction from the generator and latches the selected microinstruction in a microinstruction register (70). The initial microinstruction from the generator is first latched into the register and executed while a succeeding microinstruction is read out of the memory.

公开(公告)号：US5559985A

公开(公告)日：1996-09-24

申请号：US115223

申请日：1993-09-01

申请人： Kouji Maemura

发明人： Kouji Maemura

IPC分类号： G06F12/12 ,  G06F12/08 ,  G06F15/78 ,  G06F13/14

CPC分类号： G06F12/0879

摘要： A microprocessor incorporating a cache memory unit according to the present invention sets at the register the number of bus cycles activated by the bus cycle control circuit for replacement when a miss occurs at the cache memory, through the program executed at the instruction execution unit according to whether the accessed data are contiguous or non-contiguous. The number counted at the counter of the activated bus cycles and the number set and held at the register are compared by the comparer. The comparer outputs the replacement completion signal when they are identical. The cache control circuit outputs the replacement request signal to request bus cycle activation to the bus cycle control circuit until receipt of the replacement completion signal from the comparer.

摘要翻译： 根据本发明的并入高速缓冲存储器单元的微处理器通过根据指令执行单元执行的程序在寄存器处设置由总线周期控制电路激活的用于替换的总线周期数， 访问的数据是连续的还是不连续的。 激活的总线周期的计数器上计数的数字和设置并保存在寄存器中的数字由比较器进行比较。 比较器在相同时输出替换完成信号。 高速缓存控制电路输出替换请求信号以请求总线周期激活到总线周期控制电路，直到从比较器接收到替换完成信号。

公开(公告)号：US5544307A

公开(公告)日：1996-08-06

申请号：US283153

申请日：1994-08-03

申请人： Kouji Maemura

发明人： Kouji Maemura

IPC分类号： G06F11/28 ,  G06F11/36 ,  G06F12/08 ,  G06F9/00 ,  G06F11/00

CPC分类号： G06F11/364 ,  G06F11/3648

摘要： A microcomputer development support system for a microprocessor, includes an instruction substituting circuit tracing a memory access performed by the microprocessor and substituting a predetermined branch instruction for an instruction which is read out from a predetermined address of a user memory by the microprocessor, and a background monitor configured to give the microprocessor a memory space which is separated from the user memory but is peculiar to the microcomputer development support system. After the predetermined branch instruction has been substituted and after a break acknowledge signal informing an execution of the predetermined branch instruction has been activated, the microcomputer development support system executes a program stored in the background monitor. At the same time, the microcomputer puts the cache memory into the "cache off" condition when it starts to execute the program of the background monitor. When the execution of the program of the background monitor is terminated, the microcomputer returns the cache memory into the "cache on" condition.

摘要翻译： 一种用于微处理器的微机开发支持系统，包括一个指令替代电路，跟踪由微处理器执行的存储器访问，并且用预定的分支指令代替由微处理器从用户存储器的预定地址读出的指令，以及背景 监视器被配置为向微处理器提供与用户存储器分离但是是微型计算机显影支持系统特有的存储器空间。 在预定分支指令已被替换之后，并且在通知执行预定分支指令的中断确认信号已被激活之后，微机开发支持系统执行存储在后台监视器中的程序。 同时，当微处理器开始执行背景监视器的程序时，微型计算机将缓存器置于“缓存关闭”状态。 当后台监视器的程序的执行终止时，微计算机将高速缓冲存储器返回到“高速缓存”状态。

公开(公告)号：US5421026A

公开(公告)日：1995-05-30

申请号：US220936

申请日：1994-03-31

申请人： Yoshikuni Sato ,  Kouji Maemura

发明人： Yoshikuni Sato ,  Kouji Maemura

IPC分类号： G06F9/38 ,  G06F9/34 ,  G06F12/12 ,  G06F15/78

CPC分类号： G06F9/3846

摘要： A data processor includes a first circuit for decoding a sequence of instruction including a conditional branch instruction in such a manner that said conditional branch instruction is decoded and an instruction fetched after said conditional branch instruction is decoded before a branch condition for said conditional branch instruction has not decided. Said first circuit generates an operand address for the decoded instruction and a first signal indicating that said operand address is one generated before a branch condition is decided. A second circuit generates, after decision of said branch condition, a second signal indicating whether or not an instruction decoded after said conditional branch instruction is executed. The bus interface circuit performs replacement of a content of an associative memory. A control circuit receives the first and second signals and operates to hold replacement of a content of the associative memory.

摘要翻译： 数据处理器包括：第一电路，用于解码包括条件转移指令的指令序列，其中所述条件转移指令被解码，并且在所述条件转移指令的转移条件在所述条件转移指令的转移条件具有 没有决定 所述第一电路产生用于解码指令的操作数地址，以及指示所述操作数地址是在决定分支条件之前生成的地址的第一信号。 第二电路在判定所述分支条件之后产生指示在执行所述条件转移指令之后解码的指令的第二信号。 总线接口电路执行关联存储器的内容的替换。 控制电路接收第一和第二信号并且操作以保持关联存储器的内容的替换。