公开(公告)号：US20110042777A1

公开(公告)日：2011-02-24

申请号：US12542721

申请日：2009-08-18

Applicant: You-Di Jhang ,  Chun-Yao Huang ,  Kuo-Hua Ho

Inventor： You-Di Jhang ,  Chun-Yao Huang ,  Kuo-Hua Ho

IPC: H01L29/06

CPC classification number: H01L21/76232

Abstract: A deep trench isolation structure including a deep trench disposed within a substrate to surround an active area on the substrate and a dielectric material filled within the deep trench. The deep trench comprises at least a corner in an arc shape layout or in a polygonal line shape layout. Accordingly, the deep trench isolation structure can be obtained in a better stress condition and with less process time for trench filling.

Abstract translation: 深沟槽隔离结构，其包括设置在衬底内的深沟槽，以围绕衬底上的有源区域和填充在深沟槽内的电介质材料。 深沟槽至少包括弧形布局或折线形布置的角部。 因此，可以在更好的应力条件下获得深沟槽隔离结构，并且沟槽填充的处理时间较短。

公开(公告)号：US06440818B1

公开(公告)日：2002-08-27

申请号：US09828789

申请日：2001-04-10

Applicant: Yuan-Li Tsai ,  Kuo-Hua Ho ,  Kai-Jen Ko ,  Cheng-Hui Chung

Inventor： Yuan-Li Tsai ,  Kuo-Hua Ho ,  Kai-Jen Ko ,  Cheng-Hui Chung

IPC: H01L2176

CPC classification number: H01L21/76202 ,  H01L21/31111 ,  H01L21/31116

Abstract: A semiconductor wafer includes a silicon substrate, an active area positioned on the silicon substrate, and a field oxide layer positioned on the surface of the silicon substrate surrounding the active area. The present invention forms a doped area in the silicon substrate and within the active area and then deposits a dielectric layer on the surface of the semiconductor wafer. A dry etching process is performed to remove the dielectric layer. The top power of the dry etching process ranges between three hundred and five hundred watts to prevent damage to the silicon substrate near the field oxide layer and within the active area by the dry etching process, and to reduce the leakage current of the doped area. Additionally, the present invention also uses a wet etching process to remove the dielectric layer, which prevents an anisotropic physical impact on the silicon substrate near the field oxide layer to reduce the leakage current of the doped area.

Abstract translation: 半导体晶片包括硅衬底，位于硅衬底上的有源区域和位于围绕有源区域的硅衬底表面上的场氧化物层。 本发明在硅​​衬底中并在有源区内形成掺杂区，然后在半导体晶片的表面上沉积介电层。 进行干蚀刻处理以去除电介质层。 干蚀刻工艺的最大功率范围在三百五百瓦特之间，以防止通过干蚀刻工艺在场氧化物层附近和有源区域内的硅衬底损坏，并减少掺杂区域的漏电流。 此外，本发明还使用湿式蚀刻工艺来去除电介质层，这防止了在场氧化物层附近的硅衬底上的各向异性物理冲击以减少掺杂区域的漏电流。