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公开(公告)号：US08510690B2
公开(公告)日：2013-08-13
申请号：US12777226
申请日：2010-05-10
CPC分类号： G06F17/5081 , G06F17/5036
摘要： A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the repeated pattern and adjusted for local conditions. In another embodiment, a circuit layout is converted into a number of tiles, wherein the resistance and capacitance calculations made for the circuit elements in the center and a boundary region of the tiles are computed separately and combined. Environmental information that affects electrical interaction between circuit elements in different levels of hierarchy is calculated at a lower level of hierarchy so that such calculations do not need to be made for each placement of a repeated cell and so that not all interacting elements need to be promoted to the same hierarchy level to compute the electrical interactions.
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公开(公告)号：US07412675B2
公开(公告)日：2008-08-12
申请号：US11202935
申请日：2005-08-12
CPC分类号： G06F17/5081 , G06F17/5036
摘要： A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the repeated pattern and adjusted for local conditions. In another embodiment, a circuit layout is converted into a number of tiles, wherein the resistance and capacitance calculations made for the circuit elements in the center and a boundary region of the tiles are computed separately and combined. Environmental information that affects electrical interaction between circuit elements in different levels of hierarchy is calculated at a lower level of hierarchy so that such calculations do not need to be made for each placement of a repeated cell and so that not all interacting elements need to be promoted to the same hierarchy level to compute the electrical interactions.
摘要翻译： 计算集成电路布局中的电路元件的电学相互作用的方法，而不使整个描述布局的数据库变平坦。 在一个实施例中，分析分层数据库，并且在重复模式的每个实例处重新使用针对重复模式元素进行的电阻和电容计算，并根据局部条件进行调整。 在另一个实施例中，将电路布局转换成多个瓦片，其中对瓦片的中心的电路元件和瓦片的边界区域进行的电阻和电容计算分别计算并组合。 影响不同级别层次的电路元件之间的电气相互作用的环境信息是在较低级别的层次上进行计算，因此不需要对重复单元格的每个放置进行此类计算，因此不需要促进所有相互作用的元素 到相同的层次级别来计算电相互作用。
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公开(公告)号：US06931613B2
公开(公告)日：2005-08-16
申请号：US10180956
申请日：2002-06-24
CPC分类号： G06F17/5081 , G06F17/5036
摘要： A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the repeated pattern and adjusted for local conditions. In another embodiment, a circuit layout is converted into a number of tiles, wherein the resistance and capacitance calculations made for the circuit elements in the center and a boundary region of the tiles are computed separately and combined. Environmental information that affects electrical interaction between circuit elements in different levels of hierarchy is calculated at a lower level of hierarchy so that such calculations do not need to be made for each placement of a repeated cell and so that not all interacting elements need to be promoted to the same hierarchy level to compute the electrical interactions.
摘要翻译： 计算集成电路布局中的电路元件的电学相互作用的方法，而不使整个描述布局的数据库变平坦。 在一个实施例中，分析分层数据库，并且在重复模式的每个实例处重新使用针对重复模式元素进行的电阻和电容计算，并根据局部条件进行调整。 在另一个实施例中，将电路布局转换成多个瓦片，其中对瓦片的中心的电路元件和瓦片的边界区域进行的电阻和电容计算分别计算并组合。 影响不同级别层次的电路元件之间的电气相互作用的环境信息是在较低级别的层次上进行计算，因此不需要对重复单元格的每个放置进行此类计算，因此不需要促进所有相互作用的元素 到相同的层次级别来计算电相互作用。
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公开(公告)号：US20100223583A1
公开(公告)日：2010-09-02
申请号：US12777226
申请日：2010-05-10
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036
摘要： A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the repeated pattern and adjusted for local conditions. In another embodiment, a circuit layout is converted into a number of tiles, wherein the resistance and capacitance calculations made for the circuit elements in the center and a boundary region of the tiles are computed separately and combined. Environmental information that affects electrical interaction between circuit elements in different levels of hierarchy is calculated at a lower level of hierarchy so that such calculations do not need to be made for each placement of a repeated cell and so that not all interacting elements need to be promoted to the same hierarchy level to compute the electrical interactions.
摘要翻译： 计算集成电路布局中的电路元件的电学相互作用的方法，而不使整个描述布局的数据库变平坦。 在一个实施例中，分析分层数据库，并且在重复模式的每个实例处重新使用针对重复模式元素进行的电阻和电容计算，并根据局部条件进行调整。 在另一个实施例中，将电路布局转换成多个瓦片，其中对瓦片的中心的电路元件和瓦片的边界区域进行的电阻和电容计算分别计算并组合。 影响不同级别层次的电路元件之间的电气相互作用的环境信息是在较低级别的层次上进行计算，因此不需要对重复单元格的每个放置进行此类计算，因此不需要促进所有相互作用的元素 到相同的层次级别来计算电相互作用。
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公开(公告)号：US07716614B2
公开(公告)日：2010-05-11
申请号：US12177018
申请日：2008-07-21
CPC分类号： G06F17/5081 , G06F17/5036
摘要： A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the repeated pattern and adjusted for local conditions. In another embodiment, a circuit layout is converted into a number of tiles, wherein the resistance and capacitance calculations made for the circuit elements in the center and a boundary region of the tiles are computed separately and combined. Environmental information that affects electrical interaction between circuit elements in different levels of hierarchy is calculated at a lower level of hierarchy so that such calculations do not need to be made for each placement of a repeated cell and so that not all interacting elements need to be promoted to the same hierarchy level to compute the electrical interactions.
摘要翻译： 计算集成电路布局中的电路元件的电学相互作用的方法，而不使整个描述布局的数据库变平坦。 在一个实施例中，分析分层数据库，并且在重复模式的每个实例处重新使用针对重复模式元素进行的电阻和电容计算，并根据局部条件进行调整。 在另一个实施例中，将电路布局转换成多个瓦片，其中对瓦片的中心的电路元件和瓦片的边界区域进行的电阻和电容计算分别计算并组合。 影响不同级别层次的电路元件之间的电气相互作用的环境信息是在较低级别的层次上进行计算，因此不需要对重复单元格的每个放置进行此类计算，因此不需要促进所有相互作用的元素 到相同的层次级别来计算电相互作用。
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公开(公告)号：US20090007039A1
公开(公告)日：2009-01-01
申请号：US12177018
申请日：2008-07-21
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036
摘要： A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the repeated pattern and adjusted for local conditions. In another embodiment, a circuit layout is converted into a number of tiles, wherein the resistance and capacitance calculations made for the circuit elements in the center and a boundary region of the tiles are computed separately and combined. Environmental information that affects electrical interaction between circuit elements in different levels of hierarchy is calculated at a lower level of hierarchy so that such calculations do not need to be made for each placement of a repeated cell and so that not all interacting elements need to be promoted to the same hierarchy level to compute the electrical interactions.
摘要翻译： 计算集成电路布局中的电路元件的电学相互作用的方法，而不使整个描述布局的数据库变平坦。 在一个实施例中，分析分层数据库，并且在重复模式的每个实例处重新使用针对重复模式元素进行的电阻和电容计算，并根据局部条件进行调整。 在另一个实施例中，将电路布局转换成多个瓦片，其中对瓦片的中心的电路元件和瓦片的边界区域进行的电阻和电容计算分别计算并组合。 影响不同级别层次的电路元件之间的电气相互作用的环境信息是在较低级别的层次上进行计算，因此不需要对重复单元格的每个放置进行此类计算，因此不需要促进所有相互作用的元素 到相同的层次级别来计算电相互作用。
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