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    Method and apparatus for managing erase count of memory device
    1.
    发明授权
    Method and apparatus for managing erase count of memory device 有权
    用于管理存储器件的擦除次数的方法和装置

    公开(公告)号：US08504760B2

    公开(公告)日：2013-08-06

    申请号：US12948157

    申请日：2010-11-17

    申请人： Hak-yong Lee ,  Byoung-sul Kim ,  Kwang-won Park ,  Jun-ho Jo

    发明人： Hak-yong Lee ,  Byoung-sul Kim ,  Kwang-won Park ,  Jun-ho Jo

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0246 ,  G06F2212/7211 ,  G11C16/349

    摘要： A non-volatile memory device having a hidden cell located separate from data storage cells, and a method of effectively managing an erase count of the non-volatile memory device. The method includes preparing the non-volatile memory device that includes a hidden cell located separate from data storage cells and is not accessible to users of the data storage cells, and increasing an erase count stored in an erase count storing region of the hidden cell corresponding to at least one erased data storage cell when the at least one data storage cell is erased.

    摘要翻译： 具有与数据存储单元分离的隐藏单元的非易失性存储器件，以及有效地管理非易失性存储器件的擦除计数的方法。 该方法包括准备非易失性存储器件，该非易失性存储器件包括与数据存储单元分离的隐藏单元，并且数据存储单元的用户不可访问，并且增加存储在隐藏单元对应的擦除计数存储区域中的擦除计数 至少一个擦除的数据存储单元，当所述至少一个数据存储单元被擦除时。

    METHOD AND APPARATUS FOR MANAGING ERASE COUNT OF MEMORY DEVICE
    3.
    发明申请
    METHOD AND APPARATUS FOR MANAGING ERASE COUNT OF MEMORY DEVICE 有权
    用于管理存储器件擦除次数的方法和装置

    公开(公告)号：US20110131368A1

    公开(公告)日：2011-06-02

    申请号：US12948157

    申请日：2010-11-17

    申请人： Hak-yong Lee ,  Byoung-sul Kim ,  Kwang-won Park ,  Jun-ho Jo

    发明人： Hak-yong Lee ,  Byoung-sul Kim ,  Kwang-won Park ,  Jun-ho Jo

    IPC分类号： G06F12/00 ,  G11C16/16 ,  G11C16/04 ,  G06F12/02

    CPC分类号： G06F12/0246 ,  G06F2212/7211 ,  G11C16/349

    摘要： A non-volatile memory device having a hidden cell located separate from data storage cells, and a method of effectively managing an erase count of the non-volatile memory device. The method includes preparing the non-volatile memory device that includes a hidden cell located separate from data storage cells and is not accessible to users of the data storage cells, and increasing an erase count stored in an erase count storing region of the hidden cell corresponding to at least one erased data storage cell when the at least one data storage cell is erased.

    摘要翻译： 具有与数据存储单元分离的隐藏单元的非易失性存储器件，以及有效地管理非易失性存储器件的擦除计数的方法。 该方法包括准备非易失性存储器件，该非易失性存储器件包括与数据存储单元分离的隐藏单元，并且数据存储单元的用户不可访问，并且增加存储在隐藏单元对应的擦除计数存储区域中的擦除计数 至少一个擦除的数据存储单元，当所述至少一个数据存储单元被擦除时。

    Flash memory devices including multiple dummy cell array regions
    4.
    发明授权
    Flash memory devices including multiple dummy cell array regions 有权
    闪存器件包括多个虚拟单元阵列区域

    公开(公告)号：US07333367B2

    公开(公告)日：2008-02-19

    申请号：US11602645

    申请日：2006-11-21

    申请人： Chang-Hyun Lee ,  Jung-In Han ,  Kwang-Won Park

    发明人： Chang-Hyun Lee ,  Jung-In Han ,  Kwang-Won Park

    IPC分类号： G11C16/06 ,  G11C16/04

    CPC分类号： G11C7/14 ,  G11C16/16

    摘要： Methods for erasing an integrated circuit memory device having a cell array region that includes a main cell array region, a first dummy cell array region on a first side of the main cell array region and a second dummy cell array region on a second side of the main cell array region are provided. A first erasure voltage is applied to a plurality of main control gate electrodes in the main cell array region. The plurality of main control gate electrodes include a first outermost main control gate electrode adjacent to the first dummy cell array region and a second outermost main control gate electrode adjacent to the second dummy cell array region. A second erasure voltage is applied to an integrated circuit substrate in the main cell array region. The second erasure voltage is greater than the first erasure voltage. A third erasure voltage is applied to a first inner dummy control gate electrode adjacent to the first outermost main control gate electrode and a second inner dummy control gate electrode adjacent to the second outermost main control gate electrode. The third erasure voltage is less than the second erasure voltage. Related devices are also provided.

    摘要翻译： 用于擦除具有包括主单元阵列区域的单元阵列区域，在主单元阵列区域的第一侧上的第一虚设单元阵列区域和第二虚拟单元阵列区域的集成电路存储器件的方法， 提供主单元阵列区域。 第一擦除电压被施加到主单元阵列区域中的多个主控制栅电极。 多个主控制栅极包括与第一虚设单元阵列区域相邻的第一最外侧主控制栅电极和与第二虚设单元阵列区域相邻的第二最外侧主控制栅电极。 第二擦除电压被施加到主单元阵列区域中的集成电路基板。 第二擦除电压大于第一擦除电压。 第三擦除电压被施加到与第一最外面的主控制栅电极相邻的第一内部虚拟控制栅电极和与第二最外面的主控制栅电极相邻的第二内部虚拟控制栅电极。 第三擦除电压小于第二擦除电压。 还提供了相关设备。

    Flash memory devices including multiple dummy cell array regions
    5.
    发明申请
    Flash memory devices including multiple dummy cell array regions 有权
    闪存器件包括多个虚拟单元阵列区域

    公开(公告)号：US20070064498A1

    公开(公告)日：2007-03-22

    申请号：US11602645

    申请日：2006-11-21

    申请人： Chang-Hyun Lee ,  Jung-In Han ,  Kwang-Won Park

    发明人： Chang-Hyun Lee ,  Jung-In Han ,  Kwang-Won Park

    IPC分类号： G11C16/04

    CPC分类号： G11C7/14 ,  G11C16/16

    摘要： Methods for erasing an integrated circuit memory device having a cell array region that includes a main cell array region, a first dummy cell array region on a first side of the main cell array region and a second dummy cell array region on a second side of the main cell array region are provided. A first erasure voltage is applied to a plurality of main control gate electrodes in the main cell array region. The plurality of main control gate electrodes include a first outermost main control gate electrode adjacent to the first dummy cell array region and a second outermost main control gate electrode adjacent to the second dummy cell array region. A second erasure voltage is applied to an integrated circuit substrate in the main cell array region. The second erasure voltage is greater than the first erasure voltage. A third erasure voltage is applied to a first inner dummy control gate electrode adjacent to the first outermost main control gate electrode and a second inner dummy control gate electrode adjacent to the second outermost main control gate electrode. The third erasure voltage is less than the second erasure voltage. Related devices are also provided.

    摘要翻译： 用于擦除具有包括主单元阵列区域的单元阵列区域，在主单元阵列区域的第一侧上的第一虚设单元阵列区域和第二虚拟单元阵列区域的集成电路存储器件的方法， 提供主单元阵列区域。 第一擦除电压被施加到主单元阵列区域中的多个主控制栅电极。 多个主控制栅极包括与第一虚设单元阵列区域相邻的第一最外侧主控制栅电极和与第二虚设单元阵列区域相邻的第二最外侧主控制栅电极。 第二擦除电压被施加到主单元阵列区域中的集成电路基板。 第二擦除电压大于第一擦除电压。 第三擦除电压被施加到与第一最外面的主控制栅电极相邻的第一内部虚拟控制栅电极和与第二最外面的主控制栅电极相邻的第二内部虚拟控制栅电极。 第三擦除电压小于第二擦除电压。 还提供了相关设备。

    Methods of fabricating flash memory devices including multiple dummy cell array regions
    6.
    发明授权
    Methods of fabricating flash memory devices including multiple dummy cell array regions 有权
    制造包括多个虚拟单元阵列区域的闪速存储器件的方法

    公开(公告)号：US07158419B2

    公开(公告)日：2007-01-02

    申请号：US10918966

    申请日：2004-08-16

    申请人： Chang-Hyun Lee ,  Jung-In Han ,  Kwang-Won Park

    发明人： Chang-Hyun Lee ,  Jung-In Han ,  Kwang-Won Park

    IPC分类号： G11C16/04 ,  G11C16/06

    CPC分类号： G11C7/14 ,  G11C16/16

    摘要： Methods for erasing an integrated circuit memory device having a cell array region that includes a main cell array region, a first dummy cell array region on a first side of the main cell array region and a second dummy cell array region on a second side of the main cell array region are provided. A first erasure voltage is applied to a plurality of main control gate electrodes in the main cell array region. The plurality of main control gate electrodes include a first outermost main control gate electrode adjacent to the first dummy cell array region and a second outermost main control gate electrode adjacent to the second dummy cell array region. A second erasure voltage is applied to an integrated circuit substrate in the main cell array region. The second erasure voltage is greater than the first erasure voltage. A third erasure voltage is applied to a first inner dummy control gate electrode adjacent to the first outermost main control gate electrode and a second inner dummy control gate electrode adjacent to the second outermost main control gate electrode. The third erasure voltage is less than the second erasure voltage. Related devices are also provided.

    摘要翻译： 用于擦除具有包括主单元阵列区域的单元阵列区域，在主单元阵列区域的第一侧上的第一虚设单元阵列区域和第二虚拟单元阵列区域的集成电路存储器件的方法， 提供主单元阵列区域。 第一擦除电压被施加到主单元阵列区域中的多个主控制栅电极。 多个主控制栅极包括与第一虚设单元阵列区域相邻的第一最外侧主控制栅电极和与第二虚设单元阵列区域相邻的第二最外侧主控制栅电极。 第二擦除电压被施加到主单元阵列区域中的集成电路基板。 第二擦除电压大于第一擦除电压。 第三擦除电压被施加到与第一最外面的主控制栅电极相邻的第一内部虚拟控制栅电极和与第二最外面的主控制栅电极相邻的第二内部虚拟控制栅电极。 第三擦除电压小于第二擦除电压。 还提供了相关设备。

    Intermediate structures having reduced width contact holes that are formed during manufacture of memory cells having contact structures
    7.
    发明授权
    Intermediate structures having reduced width contact holes that are formed during manufacture of memory cells having contact structures 失效
    在具有接触结构的存储器单元的制造期间形成的具有减小的宽度接触孔的中间结构

    公开(公告)号：US08178928B2

    公开(公告)日：2012-05-15

    申请号：US12765116

    申请日：2010-04-22

    申请人： Hyun-Chul Shin ,  Jeong-Ho Park ,  Jung-Young Lee ,  Kwang-Won Park

    发明人： Hyun-Chul Shin ,  Jeong-Ho Park ,  Jung-Young Lee ,  Kwang-Won Park

    IPC分类号： H01L23/48

    CPC分类号： H01L27/11521 ,  H01L21/76831 ,  H01L21/76897 ,  H01L27/115

    摘要： Intermediate structures are provided that are formed during the manufacture of a memory device. These structures include first and second spaced apart gate patterns on a semiconductor substrate. A source/drain region is provided in the semiconductor substrate between the first and second gate patterns. An etch stop layer is provided on first and second sidewalls of the first gate pattern. The first and second sidewalls face each other to define a gap region between the etch stop layer on the first sidewall and the etch stop layer on the second sidewall. A dielectric layer is provided in the gap region. Finally, a preliminary contact hole is provided in the dielectric layer.

    摘要翻译： 提供在制造存储器件期间形成的中间结构。 这些结构包括在半导体衬底上的第一和第二间隔开的栅极图案。 源极/漏极区域设置在第一和第二栅极图案之间的半导体衬底中。 蚀刻停止层设置在第一栅极图案的第一和第二侧壁上。 第一和第二侧壁彼此面对以限定第一侧壁上的蚀刻停止层和第二侧壁上的蚀刻停止层之间的间隙区域。 在间隙区域设置介电层。 最后，在电介质层中设置预接触孔。

    Memory Cells Having Contact Structures and Related Intermediate Structures
    8.
    发明申请
    Memory Cells Having Contact Structures and Related Intermediate Structures 失效
    具有接触结构和相关中间结构的记忆单元

    公开(公告)号：US20100200926A1

    公开(公告)日：2010-08-12

    申请号：US12765116

    申请日：2010-04-22

    申请人： Hyun-Chul Shin ,  Jeong-Ho Park ,  Jung-Young Lee ,  Kwang-Won Park

    发明人： Hyun-Chul Shin ,  Jeong-Ho Park ,  Jung-Young Lee ,  Kwang-Won Park

    IPC分类号： H01L27/088

    CPC分类号： H01L27/11521 ,  H01L21/76831 ,  H01L21/76897 ,  H01L27/115

    摘要： Intermediate structures are provided that are formed during the manufacture of a memory device. These structures include first and second spaced apart gate patterns on a semiconductor substrate. A source/drain region is provided in the semiconductor substrate between the first and second gate patterns. An etch stop layer is provided on first and second sidewalls of the first gate pattern. The first and second sidewalls face each other to define a gap region between the etch stop layer on the first sidewall and the etch stop layer on the second sidewall. A dielectric layer is provided in the gap region. Finally, a preliminary contact hole is provided in the dielectric layer.

    摘要翻译： 提供在制造存储器件期间形成的中间结构。 这些结构包括在半导体衬底上的第一和第二间隔开的栅极图案。 源极/漏极区域设置在第一和第二栅极图案之间的半导体衬底中。 蚀刻停止层设置在第一栅极图案的第一和第二侧壁上。 第一和第二侧壁彼此面对以限定第一侧壁上的蚀刻停止层和第二侧壁上的蚀刻停止层之间的间隙区域。 在间隙区域设置介电层。 最后，在电介质层中设置预接触孔。

    Semiconductor packages
    10.
    发明授权
    Semiconductor packages 有权
    半导体封装

    公开(公告)号：US08618540B2

    公开(公告)日：2013-12-31

    申请号：US13118948

    申请日：2011-05-31

    申请人： Jun-Ho Jo ,  Byoung-Sul Kim ,  Kwang-Won Park ,  Hak-Yong Lee

    发明人： Jun-Ho Jo ,  Byoung-Sul Kim ,  Kwang-Won Park ,  Hak-Yong Lee

    IPC分类号： H01L23/58

    CPC分类号： G11C5/02 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided are a semiconductor package, a semiconductor memory module including the semiconductor package, and a system including the semiconductor memory module. The semiconductor package may include a plurality of main terminals arranged on a surface of the semiconductor package with constant intervals, and the plurality of main terminals may include terminals of a first set including a plurality of input/output terminals to which test signals may be input, and terminals of a second set including a plurality of input/output terminals to/from which signals other than the test signals may be input/output.

    摘要翻译： 提供半导体封装，包括半导体封装的半导体存储器模块和包括半导体存储器模块的系统。 半导体封装可以包括以恒定间隔布置在半导体封装的表面上的多个主端子，并且多个主端子可以包括包括可以输入测试信号的多个输入/输出端子的第一组的端子 ，以及可以输入/输出除了测试信号之外的信号的多个输入/输出端子的第二组的端子。