Abstract:
Example embodiments of the inventive concept are directed to solid state device products, intermediate solid state devices, and methods of manufacturing and testing the same, with removable test terminals, which may permit in situ testing of one or more components of the solid state device products.
Abstract:
A fuse box for a semiconductor device is disclosed and includes a first fuse group comprising a plurality of first fuses, arranged in a first direction and having a first cutting axis, each first fuse comprising a first portion having a first fuse pitch, a second portion having a second fuse pitch smaller than the first fuse pitch, and a third portion connecting the first and second portions, a second fuse group comprising a plurality of second fuses, arranged in the first direction and having a second cutting axis, each second fuse comprising a first portion having a first fuse pitch, a second portion having a second fuse pitch smaller than the first fuse pitch, and a third portion connecting the first portion and the second portion, and a third fuse group comprising a plurality of third fuses, wherein each third fuse has either the first cutting axis or the second cutting axis, comprises a first pattern arranged in the first direction and having a first fuse pitch, and a second pattern arranged in a second direction and having a second fuse pitch smaller than the first fuse pitch, and is arranged to bypass the first fuse or the second fuse.
Abstract:
A device and method of manufacturing a fuse region are disclosed. The fuse region may include an interlayer insulating layer formed on a substrate, a plurality of fuses disposed on the interlayer insulating layer, and fuse isolation walls located between the fuses, wherein each of the fuse isolation walls may include lower and upper fuse isolation patterns.
Abstract:
A method of forming an integrated circuit device can include forming a plurality of fuse wires on an integrated circuit substrate, and forming an insulating layer on the integrated circuit substrate and on the plurality of fuse wires so that the fuse wires are between the integrated circuit substrate and the insulating layer. A plurality of fuse cutting holes can be formed in the insulating layer wherein each of the fuse cutting holes exposes a target spot on a respective one of the fuse wires, and a cross-sectional area of the fuse wires can be reduced at the exposed target spots. Related structures are also discussed.
Abstract:
A laser link structure used in semiconductor devices and a fuse box using the laser link structure preferably include a plurality of first conductive line patterns positioned in parallel at predetermined intervals, and a second conductive line pattern broadly formed on the plurality of first conductive line patterns for forming hole regions which link the second conductive line pattern to the plurality of first conductive line patterns. Preferably, at least one hole region is formed on each of the plurality of first conductive line patterns, and via holes are formed in the hole regions.
Abstract:
A device and method of manufacturing a fuse region are disclosed. The fuse region may include an interlayer insulating layer formed on a substrate, a plurality of fuses disposed on the interlayer insulating layer, and fuse isolation walls located between the fuses, wherein each of the fuse isolation walls may include lower and upper fuse isolation patterns.
Abstract:
Example embodiments of the inventive concept are directed to solid state device products, intermediate solid state devices, and methods of manufacturing and testing the same, with removable test terminals, which may permit in situ testing of one or more components of the solid state device products.
Abstract:
Provided are a semiconductor device including a fuse focus detector, a fabrication method thereof and a laser repair method. In a chip region, fuses may be formed at a first level. A fuse focus detector including first and second conductive layers may be formed in a scribe line region. The first conductive layer may be formed at the first level, while the second conductive layer may be formed at a different level. For a laser repair method, a target region may be divided into sub-regions. In one selected sub-region, the fuse focus detector may be laser scanned in a direction for a reflection light measurement providing information on a thickness of the fuse focus detector. Using the thickness information, a focus offset value of a fuse in the selected sub-region may be calculated. When the focus offset value is within an allowable range, fuse cutting may be performed.
Abstract:
Provided are a fuse box that simultaneously prevents damage caused by laser blowing and cross talk between the fuses and a method of manufacturing the same. In a fuse box having an open region in which fuses are opened by laser blowing and a bundle region in which fuse opens do not occur, a capping layer, adjacent to the open region, having a metal layer and an insulation layer covers the outermost fuses in the bundle region, thereby reducing the influence of laser blowing of fuses in the bundle region, and preventing capacitive coupling caused by the formation of a parasitic capacitor between fuse lines and an insulation layer therebetween. Accordingly, cross talk due to the capacitive coupling can be prevented, thereby enhancing the reliability of a fuse circuit. Lower fuses can be disposed in a lower layer in the bundle region, thereby forming a two-layered fuse box.
Abstract:
A fuse box of a semiconductor memory device which comprises a plurality of fuse units commonly connected to a power line, each of the fuse units comprising a first fuse connected with the power line; and a plurality of second fuses connected with the first fuse in parallel. If the second fuses are determined to be cut off, the first fuse is cut off instead of the second fuses.