公开(公告)号：US20240090560A1

公开(公告)日：2024-03-21

申请号：US18277487

申请日：2022-02-16

申请人： Kyoung Nam KIM

发明人： Kyoung Nam KIM

IPC分类号： A23N12/12 ,  B65G47/14

CPC分类号： A23N12/125 ,  B65G47/1407 ,  B65G2201/0202

摘要： Provided is a coffee roasting apparatus including a roasting portion formed in a tubular shape having a predetermined length along an advancing direction and formed to have an inner space having a set temperature to roast coffee beans; a conveying portion formed to pass through the roasting portion from the front to rear thereof and installed to be rotatable from the inside to outside of the roasting portion to repeatedly rotate along the same trajectory; and a supply portion installed at an upper side of the conveying portion at the front of the roasting portion to supply coffee beans so that one or more coffee beans continuously fall onto the conveying portion.

公开(公告)号：US08233334B2

公开(公告)日：2012-07-31

申请号：US12650980

申请日：2009-12-31

申请人： Kyoung Nam Kim ,  Beom Ju Shin

发明人： Kyoung Nam Kim ,  Beom Ju Shin

IPC分类号： G11C7/00

CPC分类号： G11C15/046 ,  G11C15/00

摘要： A Code Address Memory (CAM) cell read control circuit of a semiconductor memory device includes a CAM cell read circuit configured to read data stored in a CAM cell and to output the read data, an internal delay circuit configured to delay an externally input reset signal and to generate a number of internal command signals, and a signal generation unit configured to generate an internal ready/busy signal in response to the internal command signals. The internal ready/busy signal is generated after the externally input reset signal has reset the CAM cell read circuit.

摘要翻译： 半导体存储器件的代码地址存储器（CAM）单元读取控制电路包括：CAM单元读取电路，被配置为读取存储在CAM单元中的数据并输出读取的数据;内部延迟电路，被配置为延迟外部输入的复位信号 并且产生多个内部命令信号，以及信号生成单元，被配置为响应于内部命令信号而生成内部就绪/忙信号。 内部就绪/忙信号在外部输入复位信号复位CAM单元读取电路后产生。

公开(公告)号：US20120002487A1

公开(公告)日：2012-01-05

申请号：US12983138

申请日：2010-12-31

申请人： Kyoung Nam KIM ,  Beom Ju SHIN

发明人： Kyoung Nam KIM ,  Beom Ju SHIN

IPC分类号： G11C7/00 ,  G11C8/18

CPC分类号： G11C16/20

摘要： A nonvolatile memory apparatus includes a memory device having a configuration information storage block for storing a first configuration data group and a second configuration data group having fewer bits than the first configuration data group and a configuration information processing circuit configured to determine a majority of the first configuration data group outputted from the memory device, during a first period of a power-up operation, and determine a majority of the second configuration data group outputted from the memory device, during a second period after the first period.

摘要翻译： 非易失性存储装置包括存储装置，具有用于存储第一配置数据组的配置信息存储块和比第一配置数据组少的位的第二配置数据组，配置信息处理电路被配置为确定第一配置数据组的大部分 配置数据组在上电操作的第一周期期间从存储器件输出，并且在第一周期之后的第二周期期间确定从存储器件输出的大部分第二配置数据组。

公开(公告)号：US08059483B2

公开(公告)日：2011-11-15

申请号：US12834429

申请日：2010-07-12

申请人： Kyoung-Nam Kim ,  Ho-Youb Cho

发明人： Kyoung-Nam Kim ,  Ho-Youb Cho

IPC分类号： G11C8/00

CPC分类号： G11C8/06

摘要： An address receiving circuit for a semiconductor apparatus includes a controller that, in response to a semiconductor apparatus initialization-related command, generates a control signal having an activation cycle corresponding to the standard of cycle time of the semiconductor apparatus initialization-related command, and an address buffer that receives an address according to the control signal.

摘要翻译： 一种用于半导体装置的地址接收电路包括控制器，响应于半导体装置初始化命令，产生具有对应于半导体装置初始化命令的周期时间标准的激活周期的控制信号，以及 地址缓冲器，根据控制信号接收地址。

公开(公告)号：US20110234281A1

公开(公告)日：2011-09-29

申请号：US13152449

申请日：2011-06-03

申请人： Kyoung Nam KIM

发明人： Kyoung Nam KIM

IPC分类号： H03L7/06

CPC分类号： H03L7/0812

摘要： A delayed lock loop (DLL) circuit includes: a phase conversion control unit configured to latch and drive a phase comparison signal in response to the input of a delay enable signal, and output the driven signal as a phase conversion control signal. A phase converting unit configured to control the phase of a delay clock on the basis of the phase conversion control signal, and transmit the controlled delay clock to a delay compensating unit.

摘要翻译： 延迟锁定环路（DLL）电路包括：相位转换控制单元，被配置为响应于延迟使能信号的输入来锁存和驱动相位比较信号，并将驱动信号作为相位转换控制信号输出。 相位转换单元，被配置为基于相位转换控制信号来控制延迟时钟的相位，并将受控延迟时钟发送到延迟补偿单元。

公开(公告)号：US20110193604A1

公开(公告)日：2011-08-11

申请号：US13091544

申请日：2011-04-21

申请人： Kyoung-Nam KIM ,  Tae-Yun Kim

发明人： Kyoung-Nam KIM ,  Tae-Yun Kim

IPC分类号： H03K5/04

CPC分类号： G06F1/04 ,  H03K5/1565 ,  H03K2005/00091

摘要： A pulse control device is maintained with a constant pulse width corresponding to a change of process or temperature. The pulse control device comprises a fuse set for selectively outputting a delay increase signal and a delay decrease signal that have a different state based on a cutting or non-cutting state of a fuse on which information on a change of process is programmed, and a pulse generator provided with a plurality of delay cells with predetermined time delay for selectively increasing or decreasing the number of the plurality of delay cells depending on the delay increase signal and the delay decrease signal to generate an internal clock with a pulse width corresponding to the number of the increased or decreased delay cells.

摘要翻译： 维持脉冲控制装置，其具有对应于过程或温度变化的恒定脉冲宽度。 所述脉冲控制装置包括用于选择性地输出延迟增加信号和延迟减小信号的熔丝，所述延迟增加信号和延迟减小信号基于其上编程关于过程改变的信息的熔丝的切割或非切割状态具有不同的状态，以及 脉冲发生器，其具有预定的时间延迟的多个延迟单元，用于根据所述延迟增加信号和所述延迟减小信号选择性地增加或减少所述多个延迟单元的数量，以产生具有对应于所述数量的脉冲宽度的内部时钟 的延迟细胞增加或减少。

公开(公告)号：US07881109B2

公开(公告)日：2011-02-01

申请号：US12480962

申请日：2009-06-09

申请人： Kyoung Nam Kim

发明人： Kyoung Nam Kim

IPC分类号： G11C16/04

CPC分类号： G11C11/406 ,  G11C11/408 ,  G11C11/4094 ,  G11C2211/4065

摘要： A refresh circuit of a semiconductor memory apparatus includes a bank active signal generator configured to selectively enable a plurality of bank active signals in response to a piled signal and disable the plurality of bank active signals in response to a plurality of precharge pulses when a refresh signal is enabled; a precharge pulse generator configured to generate a plurality of preliminary precharge pulses in response to the plurality of bank active signals; a delaying unit configured to generate a plurality of preliminary delay precharge pulses by delaying the plurality of preliminary precharge pulses; and a selecting unit configured to selectively output the plurality of preliminary precharge pulses or the plurality of preliminary delay precharge pulses as the plurality of precharge pulses in response to the piled signal.

摘要翻译： 半导体存储器装置的刷新电路包括一个存储体有源信号发生器，其被配置为响应堆叠信号有选择地启用多个存储体有效信号，并且当刷新信号时响应于多个预充电脉冲禁用多个存储体有效信号 已启用 预充电脉冲发生器，被配置为响应于所述多个存储体活动信号而产生多个初步预充电脉冲; 延迟单元，被配置为通过延迟所述多个初步预充电脉冲来产生多个初步延迟预充电脉冲; 以及选择单元，被配置为响应于所述堆叠信号而选择性地输出所述多个预充电脉冲或所述多个预备延迟预充电脉冲作为所述多个预充电脉冲。

公开(公告)号：US07830188B2

公开(公告)日：2010-11-09

申请号：US12333173

申请日：2008-12-11

申请人： Kyoung-Nam Kim

发明人： Kyoung-Nam Kim

IPC分类号： H03L7/06

CPC分类号： G11C8/18 ,  H03L7/0812

摘要： A semiconductor integrated circuit includes a DLL controlling block configured to enable or disable an update enable signal by detecting a change in a voltage level of a phase detecting signal during a predetermined time when an operation enable signal and a threshold phase difference detecting signal are enabled, and a delay locked loop (DLL) circuit configured to generate an output clock signal by delaying and driving the reference clock signal and to control a frequency of a change in the delay amount of the reference clock signal in response to the update enable signal.

摘要翻译： 半导体集成电路包括DLL控制块，其被配置为通过在使能使能信号和阈值相位差检测信号被使能的预定时间期间检测相位检测信号的电压电平的变化来使能或禁止更新使能信号， 以及延迟锁定环（DLL）电路，被配置为通过延迟和驱动参考时钟信号来产生输出时钟信号，并且响应于更新使能信号控制参考时钟信号的延迟量的变化的频率。

公开(公告)号：US20100278004A1

公开(公告)日：2010-11-04

申请号：US12834429

申请日：2010-07-12

申请人： Kyoung-Nam Kim ,  Ho-Youb Cho

发明人： Kyoung-Nam Kim ,  Ho-Youb Cho

IPC分类号： G11C8/06

CPC分类号： G11C8/06

摘要： An address receiving circuit for a semiconductor apparatus includes a controller that, in response to a semiconductor apparatus initialization-related command, generates a control signal having an activation cycle corresponding to the standard of cycle time of the semiconductor apparatus initialization-related command, and an address buffer that receives an address according to the control signal.

摘要翻译： 一种用于半导体装置的地址接收电路包括控制器，响应于半导体装置初始化命令，产生具有对应于半导体装置初始化命令的周期时间标准的激活周期的控制信号，以及 地址缓冲器，根据控制信号接收地址。

公开(公告)号：US20100033218A1

公开(公告)日：2010-02-11

申请号：US12333173

申请日：2008-12-11

申请人： Kyoung Nam Kim

发明人： Kyoung Nam Kim

IPC分类号： H03L7/06

CPC分类号： G11C8/18 ,  H03L7/0812

摘要： A semiconductor integrated circuit includes a DLL controlling block configured to enable or disable an update enable signal by detecting a change in a voltage level of a phase detecting signal during a predetermined time when an operation enable signal and a threshold phase difference detecting signal are enabled, and a delay locked loop (DLL) circuit configured to generate an output clock signal by delaying and driving the reference clock signal and to control a frequency of a change in the delay amount of the reference clock signal in response to the update enable signal.

摘要翻译： 半导体集成电路包括DLL控制块，其被配置为通过在使能使能信号和阈值相位差检测信号被使能的预定时间期间检测相位检测信号的电压电平的变化来启用或禁用更新使能信号， 以及延迟锁定环（DLL）电路，被配置为通过延迟和驱动参考时钟信号来产生输出时钟信号，并且响应于更新使能信号控制参考时钟信号的延迟量的变化的频率。