Abstract:
A digital shift register contains a succession of master-slave flipflops (M/S) which are controlled by a clock signal (H), and also comprises, at least between two master-slave flipflops (M/S), a switching device (C) which enables selection of a serial loading mode or a parallel loading mode for the preceding flipflop. The switching device (C) contains a differential stage (Cs) which is used in the serial mode and which is composed of a pair of transistors (T1, T2), and a differential stage (Cp) which is used in the parallel mode and which consists of at least two differential pairs of transistors (T3, T4 and T3', T4') which are connected in parallel, only a part of the transistors of the output branch (T4') being connected to the input of the flipflop which succeeds the switching device, so that saturation of the input transistor (Te) of this flipflop (M/S) in the parallel loading mode is avoided.
Abstract:
A method of transcoding digital data which, at the start, appear in the form of a thermometric code, the successive values of which may be represented by a first bit matrix (columns 1 to 8). The method uses an intermediate code defined by a second matrix (low significance), (columns (1), (2), (3) and (4)), and by a third matrix (high significance), (columns 4 and 8), which is extracted from the first matrix. The intermediate code delivers digital words which are shorter than the starting words and permits a later transformation into a binary code (columns [1], [2], [3], [4],) which is very simple. A decoder and a converter using this method is described where the decoder is organized so as to first produce the values of the intermediate code and then, the corresponding values in binary code. The converter employs analog gates with multiple inputs instead of the purely logic input blocks of the decoder.